參數(shù)資料
型號(hào): XC2S100E-6TQ144C
廠商: Xilinx Inc
文件頁(yè)數(shù): 78/108頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 1.8V 600 CLB'S 144-TQFP
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 600
邏輯元件/單元數(shù): 2700
RAM 位總計(jì): 40960
輸入/輸出數(shù): 102
門數(shù): 100000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
其它名稱: 122-1206
DS077-4 (v3.0) August 9, 2013
71
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O, L6P
0
C7
XC2S50E,
200E, 300E,
400E
-
I/O, L6N
0
B7
XC2S50E,
200E, 300E,
400E
-
I/O
0
A6
-
I/O, L5P
0
B6
XC2S50E,
100E, 200E,
300E, 400E
-
I/O, L5N
0
C6
XC2S50E,
100E, 200E,
300E, 400E
-
I/O, L4P
0
A5
XC2S50E,
100E, 200E,
300E, 400E
-
I/O, L4N
0
B5
XC2S50E,
100E, 200E,
300E, 400E
XC2S100E,
150E, 200E,
300E, 400E
I/O, L3P
0
D6
XC2S50E,
100E, 300E
-
I/O, L3N
0
E6
XC2S50E,
100E, 300E
-
I/O, L2P_YY
0
D5
All
-
I/O, VREF
Bank 0,
L2N_YY
0
C5
All
I/O, L1P_YY
0
B4
All
-
I/O, L1N_YY
0
C4
All
-
I/O, L0P_YY
0
A4
All
-
I/O, L0N_YY
0
A3
All
XC2S200E,
300E, 400E
I/O
0
B3
-
TCK
-
A2
-
Notes:
1.
Although designated with the _YY suffix in the XC2S50E,
XC2S100E, XC2S150E, XC2S200E, and XC2S300E, these
differential pairs are not asynchronous in the XC2S400E.
2.
There is no pair L37.
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Function
Bank
FT256 Differential Clock Pins
Clock
Bank
P
N
Pin
Name
Pin
Name
GCK0
4
T9
GCK0, I
R9
I/O (DLL),
L52P
GCK1
5
T8
GCK1, I
R8
I/O (DLL),
L52N
GCK2
1
B8
GCK2, I
A8
I/O (DLL),
L8P
GCK3
0
C8
GCK3, I
D8
I/O (DLL),
L8N
Additional FT256 Package Pins
VCCINT Pins
C3
C14
D4
D13
E5
E12
M5
M12
N4
N13
P3
P14
-
VCCO Bank 0 Pins
E8
F7
F8
-
VCCO Bank 1 Pins
E9
F9
F10
-
VCCO Bank 2 Pins
G11
H11
H12
-
VCCO Bank 3 Pins
J11
J12
K11
-
VCCO Bank 4 Pins
L9
L10
M9
-
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