參數(shù)資料
型號(hào): XC167CI
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller Preliminary
中文描述: 16位單片機(jī)的初步
文件頁(yè)數(shù): 31/80頁(yè)
文件大小: 2477K
代理商: XC167CI
XC167
Derivatives
Functional Description
Data Sheet
27
V1.1, 2003-06
Preliminary
The XC167 also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 5
shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 5
Exception Condition
Hardware Trap Summary
Trap
Flag
Trap
Vector
Vector
Location
1)
1)
Register VECSEG defines the segment where the vector table is located to.
Trap
Number
Trap
Priority
Reset Functions:
– Hardware Reset
– Software Reset
– W-dog Timer Overflow
Class A Hardware Traps:
– Non-Maskable Interrupt
– Stack Overflow
– Stack Underflow
– Software Break
Class B Hardware Traps:
– Undefined Opcode
– PMI Access Error
– Protected Instruction
Fault
– Illegal Word Operand
Access
Reserved
RESET
RESET
RESET
xx’0000
H
xx’0000
H
xx’0000
H
00
H
00
H
00
H
III
III
III
NMI
STKOF
STKUF
SOFTBRK
NMITRAP
STOTRAP
STUTRAP
SBRKTRAP
xx’0008
H
xx’0010
H
xx’0018
H
xx’0020
H
02
H
04
H
06
H
08
H
II
II
II
II
UNDOPC
PACER
PRTFLT
ILLOPA
BTRAP
BTRAP
BTRAP
BTRAP
xx’0028
H
xx’0028
H
xx’0028
H
xx’0028
H
0A
H
0A
H
0A
H
0A
H
I
I
I
I
[2C
H
3C
H
]
Any
[xx’0000
H
xx’01FC
H
]
in steps
of 4
H
[0B
H
0F
H
]
Any
[00
H
7F
H
]
Software Traps
– TRAP Instruction
Current
CPU
Priority
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