參數(shù)資料
型號(hào): XC167CI
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller Preliminary
中文描述: 16位單片機(jī)的初步
文件頁數(shù): 25/80頁
文件大小: 2477K
代理商: XC167CI
XC167
Derivatives
Functional Description
Data Sheet
21
V1.1, 2003-06
Preliminary
The EBC also controls accesses to resources connected to the on-chip LXBus. The
LXBus is an internal representation of the external bus and allows accessing integrated
peripherals and modules in the same way as external components.
The TwinCAN module is connected and accessed via the LXBus.
3.3
Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Figure 4
CPU Block Diagram
Based on these hardware provisions, most of the XC167’s instructions can be executed
in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift
and rotate instructions are always processed during one machine cycle independent of
a
d
d
CSP
IP
CPUCON1
CPUCON2
CPUID
FIFO
IFU
IDX0
IDX1
QX0
QX1
QR1
QR0
SP
SPSEG
VECSEG
TFR
STKOV
STKUN
DPP0
DPP1
DPP2
DPP3
+/-
+/-
ADU
MDL
Ones
MDH
Zeros
MAL
Division Unit
Multiply Unit
MAH
Multiply Unit
MSW
MCW
ALU
RF
+/-
+/-
PSW
MRW
MDC
Barrel-Shifter
Bit-Mask-Gen.
WB
MAC
CPU
Buffer
CP
2-Stage
Prefetch
Pipeline
5-Stage
Pipeline
IPIP
DPRAM
a
data in
data out
DMU
R15
R14
R0
R1
R15
R14
R0
R1
R15
R14
R0
R1
GGGPRs
R15
R14
R0
R1
GPRs
SRAM
d
address
d
Peripheral-Bus
PMU
Internal Program Memory
System-Bus
a
d
d
System-Bus
Prefetch Unit
Branch Unit
Return Stack
Injection/Exception
Handler
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