參數(shù)資料
型號(hào): XC164TM
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller with C166SV2 Core
中文描述: 16位單片機(jī)與C166SV2核心
文件頁數(shù): 19/65頁
文件大?。?/td> 587K
代理商: XC164TM
XC164TM
Derivatives
Functional Description
Data Sheet
17
V1.0, 2005-11
3.2
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Central Processing Unit (CPU)
Figure 3-2
CPU Block Diagram
Based on these hardware provisions, most of the XC164TM’s instructions can be
executed in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For
DPRAM
CPU
IPIP
RF
R0
R1
GPRs
R14
R0
R1
R0
RR15
IFU
Injection/
Exception
Handler
ADU
MAC
mca04917_x.vsd
CPUCON1
CPUCON2
CSP
IP
Return
Stack
FIFO
Branch
Unit
Prefetch
Unit
VECSEG
TFR
+/-
IDX0
IDX1
QX0
QX1
QR0
QR1
DPP0
DPP1
DPP2
DPP3
SPSEG
SP
STKOV
STKUN
+/-
MRW
MCW
MSW
MAL
+/-
MAH
Multiply
Unit
ALU
Division Unit
Multiply Unit
Bit-Mask-Gen.
Barrel-Shifter
+/-
MDC
PSW
MDH
ZEROS
MDL
ONES
R1
GPRs
R15
CP
WB
Buffer
2-Stage
Prefetch
Pipeline
5-Stage
Pipeline
R0
R1
GPRs
R14
R15
PMU
DMU
DSRAM
EBC
Peripherals
PSRAM
Flash/ROM
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PDF描述
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