參數(shù)資料
型號(hào)： XC164-32F
廠商： INFINEON TECHNOLOGIES AG
英文描述： 16-Bit Single-Chip Microcontroller with C166SV2 Core
中文描述： 16位單片機(jī)與C166SV2核心
文件頁數(shù)： 74/80頁
文件大?。?/td> 826K
代理商： XC164-32F
XC164-32
Derivatives
Electrical Parameters
Data Sheet
72
V1.0, 2005-06
Note: The shaded parameters have been verified by characterization.
They are not subject to production test.
Table 22
External Bus Cycle Timing
(Operating Conditions apply)
Parameter
Symbol
Limits
Unit
Min.
1
Max.
15
Output valid delay for:
RD, WR(L/H)
Output valid delay for:
BHE, ALE
Output valid delay for:
A23 … A16, A15 … A0 (on PORT1)
Output valid delay for:
A15 … A0 (on PORT0)
Output valid delay for:
CS
Output valid delay for:
D15 … D0 (write data, MUX-mode)
Output valid delay for:
D15 … D0 (write data, DEMUX-mode)
Output hold time for:
RD, WR(L/H)
Output hold time for:
BHE, ALE
Output hold time for:
A23 … A16, A15 … A0 (on PORT0)
Output hold time for:
CS
Output hold time for:
D15 … D0 (write data)
Input setup time for:
D15 … D0 (read data)
Input hold time
D15 … D0 (read data)
1)
tc
10
CC
ns
tc
11
CC
-1
8
ns
tc
12
CC
3
18
ns
tc
13
CC
3
18
ns
tc
14
CC
3
16
ns
tc
15
CC
3
19
ns
tc
16
CC
2
16
ns
tc
20
CC
-3
4
ns
tc
21
CC
0
11
ns
tc
23
CC
1
13
ns
tc
24
CC
-2
4
ns
tc
25
CC
1
13
ns
tc
30
SR
29
–
ns
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
tc
31
SR
-5
–
ns
相關(guān)PDF資料
PDF描述
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XC164CS-16F 16-Bit Single-Chip Microcontroller with C166SV2 Core
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