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參數(shù)資料
| 型號： | XC164-32F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
| 中文描述： | 16位單片機與C166SV2核心 |
| 文件頁數(shù)： | 69/80頁 |
| 文件大小： | 826K |
| 代理商： | XC164-32F |
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XC164-32
Derivatives
Electrical Parameters
Data Sheet
67
V1.0, 2005-06
4.4.2
On-chip Flash Operation
The XC164’s Flash module delivers data within a fixed access time (see
Table 17
).
Accesses to the Flash module are controlled by the PMI and take 1 + WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time
t
ACC
of the Flash array. Therefore, the required Flash waitstates depend on the
available speed grade as well as on the actual system frequency.
Note: The Flash access waitstates only affect non-sequential accesses. Due to
prefetching mechanisms, the performance for sequential accesses (depending on
the software structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average
performance by 5% … 15%.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), Standard devices
must be operated with 2 waitstates: ((2 + 1)
×
25 ns)
≥
70 ns.
Grade A devices can be operated with 1 waitstate: ((1 + 1)
×
25 ns)
≥
50 ns.
Table 18
indicates the interrelation of waitstates, system frequency, and speed grade.
Note: The maximum achievable system frequency is limited by the properties of the
respective derivative, i.e. 40 MHz (or 20 MHz for xxx-32F20F devices).
Table 17
Flash Characteristics
(Operating Conditions apply)
Parameter
Symbol
Limit Values
Typ.
–
–
2
2)
200
2)
Unit
Min.
–
–
–
–
Max.
70
1)
50
1)
5
500
Flash module access time (Standard)
Flash module access time (Grade A)
Programming time per 128-byte block
Erase time per sector
t
ACC
t
ACC
t
PR
t
ER
CC
CC
CC
CC
1) The actual access time is also influenced by the system frequency, so the frequency ranges are not fully linear.
See
Table 18
.
2) Programming and erase time depends on the system frequency. Typical values are valid for 40 MHz.
ns
ns
ms
ms
Table 18
Flash Access Waitstates
Required Waitstates
Frequency Range for
Standard Flash Speed
f
CPU
≤
16 MHz
f
CPU
≤
28 MHz
f
CPU
≤
40 MHz
Frequency Range for
Flash Speed Grade A
f
CPU
≤
20 MHz
f
CPU
≤
40 MHz
f
CPU
≤
40 MHz
0 WS (WSFLASH = 00
B
)
1 WS (WSFLASH = 01
B
)
2 WS (WSFLASH = 10
B
)
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