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參數(shù)資料
| 型號(hào)： | XALJ174 |
| 英文描述： | WIPPSCHALTER ZB2 STEUERGEHAEUSE TASTEN 1 |
| 中文描述： | WIPPSCHALTER ZB2 STEUERGEHAEUSE塔斯滕1 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 215K |
| 代理商： | XALJ174 |
Functionsindedicatedmemoriesinordertoreduce
the computationaltime. Thereforea great amount
ofW.A.R.P.processing is based on alook-uptable
approachrather than on on-line calculation.
Those Membership Functions (MFs), each one
portrayed by a configurable resolution of 2
6
or 2
7
elements,arestored in fourinternalRAMs (1Kbyte
each). The consequent MFs, due to the different
modelling, are loaded in a single RAM by storing
for each MF its areaand its barycentre.Thisis due
to theadoptionof the CenterofGravity defuzzifica-
tion method.
The downloading phase allows the setting of the
device, in terms of I/O number, universes of dis-
courseandMFshapes.DuringthisphaseW.A.R.P.
prepares its internal memories for the on-line
elaboration phase and loads the microcode in its
programmemory.Thismicrocode,whichdrivesthe
on-line phase, is generated by the Compiler (see
W.A.R.P.-SDT User Manual) according to the
adoptedconfiguration.Thepossibleconfigurations
areshown in table1.
During the on-line phase (up to 40MHz working
frequency),W.A.R.P.processes theinput dataand
produces its outputsaccording to theconfiguration
loadedin the downloadingphase.
W.A.R.P. is conceivedto work together with tradi-
Name
V
DD
V
SS
A0-A9
I0-I7
PRST
FIN
OFL
CHM
TE
MTE
MCLK
EPA0-EPA2
*
O0-O9
OCNT0-OCNT3
STB
EP
NP
OTST
OMTS
SYNC
Pins Type
-
-
I/O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
Function
Power Supply
Ground
Memory Address Bus
Data Input Bus
Preset
FirstInput Signal
Off-Line/On-Line Switch
Charge Mode Switch
Testing(it mustbe connected to V
SS
)
Testing(it mustbe connected to V
SS
)
Clock (up to 40 MHz)
EPROM Address Bus
Defuzzified Output
Output Counter
Strobe (Output Ready Signal)
End Process
New Process
Testing(it mustbe connected to V
SS
)
Testing(it mustbe connected to V
SS
)
External Synchronization
Table 4. Pin Description
tional microcontrollers which shall perform normal
control tasks while W.A.R.P. will be indipendently
responsiblefor all the fuzzy relatedcomputing.
W.A.R.P. is manufacturedusing the high perform-
ance, reliable HCMOS4T (O.7
μ
m) SGS-THOM-
SON Microelectronicsprocess.
PIN DESCRIPTION
V
DD
, V
SS
: Power is supplied to W.A.R.P. using
these pins.V
DD
is the power connectionand V
SS
is
the ground connection;multi-connections arenec-
essary.
A0-A9:
When the CHM pin is
low
they accept as
input theaddressesfortheinternalmemory bus.In
the off-linemodetheyareused toaddressW.A.R.P.
memories where the microprogram and data of
antecedentandconsequentmembershipfunctions
must be loaded.
Each A0-A9 word is composed byassembling the
datacontainedinthe memorysupportrelatedto.cs
and .addfiles (see W.A.R.P.-SDT User Manual). In
particular,couplesofdatarespectivelycomingfrom
.cs and .addfiles are joined to form a single A0-A9
word in the followingway:
*
Pins not used in W.A.R.P. 1.0
4/19
W.A.R.P.1.1
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