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| 型號： | VZN05 |
| 英文描述： | NOCKANSCHALTER VARIO HILFSKONTACK |
| 中文描述： | NOCKANSCHALTER巴里奧HILFSKONTACK |
| 文件頁數(shù)： | 1/19頁 |
| 文件大?。?/td> | 215K |
| 代理商： | VZN05 |
W.A.R.P. 1.1
W
EIGHT
A
SSOCIATIVE
R
ULE
P
ROCESSOR
ADVANCED DATA
HighSpeed Rules Processing
AntecedentMembership Functions with any
Shape
Up to 256 Rules (4 Antecedents,1
Consequent)
Up to 16 InputConfigurableVariables
Up to 16 MembershipFunctions foran Input
Variable
Up to 16 OutputVariables
Up to 128 Membership Functions for all
Consequents
MAX-DOT InferenceMethod
Defuzzification on chip
SoftwareTools and Emulators Availability
100-pinCPGA100Ceramic Package
84-leadPlastic LeadedChip Carrier package
GENERAL DESCRIPTION
W.A.R.P. is a VLSI Fuzzy Logic controller whose
architecture arises from the need of realizing an
integratedstructure with high inferencingperform-
ancesandflexibility. Toget those resultsa modular
architecture based on a set of parallel memory
blocks has been implemented.
In orderto obtainhighperformancesW.A.R.P.uses
different data representations during the various
phases of the computational cycle, so that it is
always operating on the optimal data repre-
sentation. A vectorial characterization has been
adopted for the Antecedent Membership Func-
tions. W.A.R.P. exploits a SGS-THOMSON pat-
entedstrategytostoretheAntecedentMembership
May 1996
This is advance informationon a new productnow in developmentor undergoingevaluation. Detailsare subject to change without notice.
8
I0-I7
A0-A9
10
O0-O9
FIN
3
CHM OFL
4
OCNT0-OCNT3
STB
EP
NP
PRST
MCLK VSS VDD
W.A.R.P.
1.1
10
EPA0-EPA2
SYNC
Figure1. Logic Diagram
Number of Inputs
Standard Rule Format
Rules Number
Antecedent’s MFs Number
Consequent’s MFs Number
Input Data Resolution
Output Data Resolution
Configurable [1..8]
4 Antecedents, 1 Consequent [or subsets]
Max 256 Rules in the 4Antecedent, 1 Consequent format
Configurable [up to16 for an inputvariable]
Max 256 for all outputs variables
8 bit
8 bit
Table 1. W.A.R.P. Configuration Settings
CPGA100
PLCC84
1/19
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