參數(shù)資料
型號: XA3S50-4PQG208I
廠商: Xilinx Inc
文件頁數(shù): 3/8頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3 50K 208-PQFP
標(biāo)準(zhǔn)包裝: 1
系列: Spartan®-3 XA
LAB/CLB數(shù): 192
邏輯元件/單元數(shù): 1728
RAM 位總計: 73728
輸入/輸出數(shù): 124
門數(shù): 50000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
Introduction and Ordering Information
DS314 (v1.3) June 18, 2009
Product Specification
3
R
Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust static memory cells that collectively control
all functional elements and routing resources. Before
powering on the FPGA, configuration data is stored
externally in a PROM or some other nonvolatile medium
either on or off the board. After applying power, the
configuration data is written to the FPGA using any of five
different modes: Master Parallel, Slave Parallel, Master
Serial, Slave Serial and Boundary Scan (JTAG). The Master
and Slave Parallel modes use an 8-bit-wide SelectMAP
port.
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 18
single-ended standards and eight differential standards as
listed in Table 2. Many standards support the DCI feature,
which uses integrated terminations to eliminate unwanted
signal reflections. Table 3 shows the number of user I/Os as
well as the number of differential I/O pairs available for each
device/package combination.
.
Figure 1: Spartan-3 Family Architecture
DS314-1_01_100808
Notes:
1.
The XA3S50 has only the block RAM column on the far left.
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