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參數(shù)資料
型號: XA3S1200E-4FTG256I
廠商: Xilinx Inc
文件頁數(shù): 16/37頁
文件大小: 0K
描述: IC FPGA SPARTAN3E 1200K 256FTBGA
標準包裝: 90
系列: Spartan®-3E XA
LAB/CLB數(shù): 8672
邏輯元件/單元數(shù): 19512
RAM 位總計: 516096
輸入/輸出數(shù): 190
門數(shù): 1200000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應商設備封裝: 256-FTBGA
DS635 (v2.0) September 9, 2009
Product Specification
23
R
Block RAM Timing
Clock Frequency
FMULT
Internal operating frequency for a two-stage 18x18 multiplier using the
AREG and BREG input registers and the PREG output register(1)
0240
MHz
Notes:
1.
Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
Table 24: 18 x 18 Embedded Multiplier Timing (Continued)
Symbol
Description
-4 Speed Grade
Units
Min
Max
Table 25: Block RAM Timing
Symbol
Description
-4 Speed Grade
Units
Min
Max
Clock-to-Output Times
TBCKO
When reading from block RAM, the delay from the active transition
at the CLK input to data appearing at the DOUT output
-2.82
ns
Setup Times
TBACK
Setup time for the ADDR inputs before the active transition at the
CLK input of the block RAM
0.38
-ns
TBDCK
Setup time for data at the DIN inputs before the active transition at
the CLK input of the block RAM
0.23
-ns
TBECK
Setup time for the EN input before the active transition at the CLK
input of the block RAM
0.77
-ns
TBWCK
Setup time for the WE input before the active transition at the CLK
input of the block RAM
1.26
-ns
Hold Times
TBCKA
Hold time on the ADDR inputs after the active transition at the CLK
input
0.14
-ns
TBCKD
Hold time on the DIN inputs after the active transition at the CLK
input
0.13
-ns
TBCKE
Hold time on the EN input after the active transition at the CLK input
0
-ns
TBCKW
Hold time on the WE input after the active transition at the CLK input
0
-ns
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