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參數(shù)資料
| 型號： | X96010V14IZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SENSOR CONDITIONER 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 95 |
| 類型： | 傳感器調(diào)節(jié)器 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 接口： | 2 線 |
| 電流 - 電源： | 15mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1246 (CN2011-ZH PDF) |
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6
FN8214.1
October 25, 2005
A/D CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions)
Notes: 1.
“LSB” is defined as V(VRef)/255, “Full Scale” is defined as V(VRef).
2.
OffsetADC: For an ideal converter, the first transition of its transfer curve occurs at
above zero. Offset error is the
amount of deviation between the measured first transition point and the ideal point.
FSErrorADC: For an ideal converter, the last transition of its transfer curve occurs at
. Full Scale Error is the
amount of deviation between the measured last transition point and the ideal point,
after subtracting the Offset from the measured curve.
DNLADC: DNL is defined as the difference between the ideal and the measured code transitions for successive A/D code outputs
expressed in LSBs. The measured transfer curve is adjusted for Offset and Fullscale errors before calculating DNL.
INLADC: The deviation of the measured transfer function of an A/D converter from the ideal transfer function. The INL error is also
defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured trans-
fer curve is adjusted for Offset and Fullscale errors before calculating INL.
3.
These parameters are periodically sampled and not 100% tested.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions / Notes
ADCTIME
A/D converter conversion
time
9
ms
Proportional to A/D converter
input voltage. This value is
maximum at full scale input
of A/D converter.
ADCfiltOff = “1”
RINADC
VSense pin input
resistance
100
k
VSense as an input,
ADCIN bit = “1”
CINADC
VSense pin input
capacitance
1
7
pF
VSense as an input,
ADCIN bit = “1”,
Frequency = 1 MHz
See note 3.
VINADC
VSense input signal range
0
V(VRef)
V
This is the A/D Converter
Dynamic Range. ADCIN bit = “1”
The ADC is monotonic
OffsetADC
A/D converter offset error
±1
LSB
See notes 1 and 2
FSErrorADC
A/D converter full scale error
±1
LSB
DNLADC
A/D Converter Differential
Nonlinearity
±0.5
LSB
INLADC
A/D converter Integral
Nonlinearity
±1
LSB
0.5 x V(VRef)
255
[]
254.5 x V(VRef)
255
[]
X96010
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