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參數(shù)資料
| 型號： | X9430WV24 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/21頁 |
| 文件大小： | 0K |
| 描述： | IC DUAL DCP + OPAMP 10K 24TSSOP |
| 標準包裝： | 75 |
| 系列： | XDCP™ |
| 接片： | 64 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 6 線 SPI（芯片選擇，設(shè)備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1238 (CN2011-ZH PDF) |
5
FN8198.0
March 11, 2005
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0 - A1 input
pins. The X9430 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9430 to successfully
continue the command sequence. The A0 - A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
Figure 1. Identification Byte Format
Instruction Byte
The next byte sent to the X9430 contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the WCRs of the two pots, and when
applicable, they point to one of four associated data
registers. The format is shown below in Figure 2.
Figure 2. Instruction Byte Format
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last bit (P0)
selects which one of the two potentiometers is to be
affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
The basic sequence of the two byte instructions is
illustrated in Figure 3. These two-byte instructions
exchange data between a wiper counter register and
one of the four data registers associated with each. A
transfer from a data register to a wiper counter register
is essentially a write to a static RAM. The response of
the wiper to this action will be delayed tWRL. A transfer
from the wiper counter register (current wiper position)
to a data register is a write to nonvolatile memory and
takes a minimum of tWR to complete. The transfer can
occur between one of the two potentiometers and one
of its associated registers; or it may occur globally,
wherein the transfer occurs between both of the poten-
tiometers and one of their associated registers.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9430; either between the host and
one of the data registers or directly between the host
and the Wiper Counter and Registers. These instruc-
tions are: 1) Read Wiper Counter Register, read the
current wiper position of the selected pot 2) Write
Wiper Counter Register, i.e. change current wiper
position of the selected pot; 3) Read Data Register,
read the contents of the selected nonvolatile register; 4)
Write Data Register, write a new value to the selected
data register; 5)Read Status, returns the contents of the
WIP bit which indicates if an internal write cycle is in
progress.
The sequence of these operations is shown in Figure
4 and Figure 5.
The final command is Increment/Decrement. It is differ-
ent from the other commands, because it’s length is
indeterminate. Once the command is issued, the master
can clock the selected wiper up and/or down in one resis-
tor segment steps; thereby, providing a fine tuning capa-
bility to the host. For each SCK clock pulse (tHIGH) while
SI is HIGH, the selected wiper will move one resistor
segment towards the VH terminal. Similarly, for each
SCK clock pulse while SI is LOW, the selected wiper will
move one resistor segment towards the VL terminal. A
detailed illustration of the sequence and timing for this
operation are shown in Figure 6 and Figure 7.
1
00
A1
A0
Device Type
Identifier
Device Address
1
I1
I2
I3
I0
R1
R0
0
P0
WCR Select
Register
Select
Instructions
X9430
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| VE-B2L-MW-B1 | CONVERTER MOD DC/DC 28V 100W |
| VI-J1B-MZ | CONVERTER MOD DC/DC 95V 25W |
| MS3456L20-4SY | CONN PLUG 4POS STRAIGHT W/SCKT |
| X9430WV24-2.7 | IC DUAL DCP + OPAMP 10K 24TSSOP |
| MS3456L20-4SX | CONN PLUG 4POS STRAIGHT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X9430WV24-2.7 | 功能描述:IC DUAL DCP + OPAMP 10K 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標準值 35 ppm/°C 存儲器類型:非易失 接口:3 線串口 電源電壓:2.7 V ~ 5.25 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN-EP（3x3） 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:1399 (CN2011-ZH PDF) 其它名稱:MAX5423ETA+TCT |
| X9430WV24I | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Dual Digitally Controlled Potentiometer (XDCP⑩) with Operational Amplifier |
| X9430WV24I-2.7 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Dual Digitally Controlled Potentiometer (XDCP⑩) with Operational Amplifier |
| X9430WV24M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| X9430WV24M2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
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