![](http://datasheet.mmic.net.cn/Intersil/X9430WS24-2-7_datasheet_99921/X9430WS24-2-7_1.png)
1
FN8198.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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| Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
PRELIMINARY
X9430
Programmable Analog
Dual Digitally Controlled Potentiometer
(XDCP) with Operational Amplifier
FEATURES
Two CMOS voltage operational amplifiers
Two digitally controlled potentiometers
Can be combined or used separately
Amplifiers
—Low voltage operation
—V+/V- = ±2.7V to ±5.5V
—Rail-to-rail CMOS performance
—1MHz gain bandwidth product
Digitally controlled potentiometer
—Dual 64 tap potentiometers
—Rtotal = 10k
—SPI serial interface
—VCC = 2.7V to 5.5V
DESCRIPTION
The X9430 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with
near rail-to-rail outputs. All pins for the two amplifiers
are brought out of the package to allow combining
them with the potentiometers or using them as com-
plete stand-alone amplifiers.
The digitally controlled potentiometers consist of a
series string of 63 polycrystalline resistors that behave
as standard integrated circuit resistors. The SPI serial
port, common to both pots, allows the user to program
the connection of the wiper output to any of the resis-
tor nodes in the series string. The wiper position is
saved in the on board E2 memory to allow for nonvola-
tile restoration of the wiper position.
A wide variety of applications can be implemented
using the potentiometers and the amplifiers. A typical
application is to implement the amplifier as a wiper
buffer in circuits that use the potentiometer as a voltage
reference. The potentiometer can also be combined
with the amplifier yielding a digitally programmable gain
amplifier or programmable current source.
BLOCK DIAGRAM
VOUT1
Control and
CS
SCK
SO
SI
A1
A0
+
–
Memory
VCC
VNI0
V+
V-
RW0
VSS
VOUT0
+
–
VNI1
VINV1
VINV0
RH0 RL0
RW1 RL1 RH1
WCR1
WCR0
WP
HOLD
Data Sheet
March 11, 2005
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