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參數(shù)資料
| 型號(hào)： | X9279UV14ZT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP SGL 256TAP 50K 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
5
FN8175.4
September 23, 2009
Power-up and Down Recommendations.
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more
positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL,
VW. The VCC ramp rate specification is always in effect.
Serial Interface Description
Serial Interface
The X9279 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9279 will be
considered a slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (see
Figure 2.
Start Condition
All commands to the X9279 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9279 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met (see Figure 2).
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 2).
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9279 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9279 will
respond with a final acknowledge (see Figure 2).
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
RH
RL
RW
8
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
WIPER
(WCR)
BANK_0 Only
(DR0)
(DR1)
(DR2)
(DR3)
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
R
X9279
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