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參數(shù)資料
| 型號： | X9119TV14Z-2.7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP SGL 1024TAP 100K 14TSSOP |
| 標(biāo)準(zhǔn)包裝： | 95 |
| 系列： | XDCP™ |
| 接片： | 1024 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
6
FN8162.4
July 9, 2008
Instruction and Register Description
Device Addressing: Identification Byte (ID and A)
Following a start condition, the master must output the
address of the slave it is accessing. The most significant four
bits of the slave address are the device type identifier. The
ID[3:0] bits is the device id for the X9119; this is fixed as
0101[B] (refer to Table 1).
The A2–A0 bits in the ID byte is the internal slave address.
The physical device address is defined by the state of the
A2–A0 input pins. The slave address is externally specified
by the user. The X9119 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9119 to successfully
continue the command sequence. Only the device which
slave address matches the incoming device address sent by
the master executes the instruction. The A2–A0 inputs can
be actively driven by CMOS input signals or tied to VCC or
VSS. The R/W bit is the LSB and is be used to program the
device for read or write operations.
INSTRUCTION BYTE AND REGISTER SELECTION
The next byte sent to the X9119 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode (IOP[2:0]). The RB
and RA bits point to one of the four registers. The format is
shown below in Table 2.
Table 3 provides a complete summary of the instruction set
opcodes.
TABLE 1. IDENTIFICATION BYTE FORMAT
TABLE 2. INSTRUCTION BYTE FORMAT
TABLE 3. INSTRUCTION SET
NOTE: 1/0 = data is one or zero.
ID3
ID2
ID1
ID0
A2
A1
A0
R/W
01
(MSB)
(LSB)
DEVICE TYPE
IDENTIFIES
INTERNAL SLAVE
ADDRESS
READ OR
WRITE BIT
I2
I1
I0
0
RB
RA
0
(MSB)
(LSB)
INSTRUCTION
OPCODE
REGISTER
SELECTION
REGISTER SELECTED
RB
RA
DR0
0
DR1
0
1
DR2
1
0
DR3
1
INSTRUCTION
INSTRUCTION SET
OPERATION
R/W
I2
I1
I0
0RB
RA
0
Read Wiper Counter
Register
1
0
Read the contents of the Wiper Counter
Register
Write Wiper Counter
Register
0
1
0
1
0
Write new value to the Wiper Counter
Register
Read Data Register
1
0
1
0
1/0
0
Read the contents of the Data Register pointed to
RB-RA.
Write Data Register
0
1
0
1/0
0
Write new value to the Data Register
pointed to RB-RA.
XFR Data Register to
Wiper Counter Register
1
0
1/0
0
Transfer the contents of the Data Register
pointed to by RB-RA.to the Wiper Counter
Register
XFR Wiper Counter Register
to Data Register
0
1
0
1/0
0
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by
RB-RA.
X9119
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