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參數(shù)資料
| 型號： | X80073 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Hot Swap Controller with Advanced Fault Protection and Voltage Refulator Output |
| 中文描述： | 熱插拔控制器與先進的故障保護和輸出電壓Refulator |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 279K |
| 代理商： | X80073 |
9
FN8150.0
March 15, 2005
PIN CONFIGURATION
FUNCTIONAL DESCRIPTION
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
bypass capacitors at the input of the board’s power module or
DC/DC converter can draw huge transient currents as they
charge up. This transient current can cause permanent
damage to the board’s components and cause transients on
the system power supply.
The X80070 is designed to turn on a board’s supply voltage in a
controlled manner (see Figure 5), allowing the board to be
safely inserted or removed from a live backplane. The device
also provides undervoltage, overvoltage and overcurrent
protection while keeping the power module (dc-dc converter)
off until the backplane input voltage is stable and within
tolerance.
Figure 5. Typical Inrush with Gate Slew Rate Control
PIN DESCRIPTIONS
Pin
Name
1
V
RGO
Description
Regulated 5V output.
Used to pull-up
user programmable inputs IGQ0, IGQ1,
BATT-ON and MRH (if needed).
Pin not used.
Do not connect to this pin.
Not Available.
Connect to V
EE
.
Not Available.
Connect to V
EE
.
Positive Supply Voltage Input.
Negative Supply Voltage Input.
Analog Undervoltage and Overvoltage
Input.
Turns off the external N-channel
MOSFET when there is an undervoltage
or overvoltage condition.
Circuit Breaker Sense Input
. This input
pin detects the overcurrent condition.
FET Gate Drive.
This pin supplies the cur-
rent to turn on the FET.
Pin not used.
Do not connect to this pin.
Pin not used.
Do not connect to this pin.
Not Available.
Connect to V
RGO
.
Not Available.
Connect to V
RGO
.
Not Available.
Connect to V
EE
.
Failure After Re-try (FAR)
output signal.
BATT-ON
Battery On Input
. This input signals that
the battery backup (or secondary supply)
is supplying power to the backplane. It has
an internal pulldown resistor. (>10M
typical)
PWRGD
Power Good Output.
This output pin en-
ables a power module.
2
3
4
5
6
7
DNC
NA2
NA2
V
DD
V
EE
V
UV/OV
SENSE
9
GATE
10
11
12
13
14
15
16
DNC
DNC
NA1
NA1
NA2
FAR
17
X80070
20L QFN Package
I
M
V
RGO
DNC
NA2
NA2
I
NA1
NA1
D
G
V
U
S
FAR
NA2
P
B
V
DD
DNC
V
E
1
2
3
4
56
7
8
9 10
11
12
13
14
16
17
18
19
20
TOP VIEW
NA1 pins connect to V
RGO
NA2 pins connect to V
EE
5mm x 5mm
18
IGQ1
Gate Current Quick Select Bit 1 Input.
This pin is used to change the gate current
drive and is intended to allow for current
ramp rate control of the gate pin of an
external FET. It has an internal pulldown
resistor. (>10M
typical)
Gate Current Quick Select Bit 0 Input.
This pin is used to change the gate current
drive and is intended to allow for current
ramp rate control of the gate pin of an
external FET. It has an internal pulldown
resistor. (>10M
typical)
Manual Reset.
Pulling the MR pin LOW
initiates a GATE pin reset (GATE pin
pulled LOW). The MR signal must be held
LOW for 5
μ
secs (minimum).
19
IGQ0
20
MR
PIN DESCRIPTIONS
(Continued)
Pin
Name
Description
V
GATE
V
FET_DRAIN
PWRGD
I
INRUSH
X80070, X80071, X80072, X80073
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