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參數(shù)資料
| 型號： | X80073 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Hot Swap Controller with Advanced Fault Protection and Voltage Refulator Output |
| 中文描述： | 熱插拔控制器與先進(jìn)的故障保護(hù)和輸出電壓Refulator |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 279K |
| 代理商： | X80073 |
12
FN8150.0
March 15, 2005
Gate Drive Output Slew Rate (Inrush Current) Control
The gate output drives an external N-Channel FET. The GATE
pin goes high when no overcurrent, undervoltage or
overvoltage conditions exist.
The X80070 provides an I
GATE
current of 50uA to provide on-
chip slew rate control to minimize inrush current and provide
the best turn on time for a given load, while avoiding
overcurrent conditions.
Slew Rate (Gate) Control
As shown in Figure 11, this circuit block contains a current
source (I
GATE
) that drives the 50uA current into the GATE pin.
This current provides a controlled slew rate for the FET.
To give the designer flexibility in the design of the hot swap
circuit, the X80070 provides two external pins, IGQ1 and IGQ0.
These pins allow the user to switch to different GATE currents
on-the-fly by selecting one of four pre-selected I
GATE
currents.
When IGQ0 and IGQ1 are left unconnected, the gate current is
50uA. The other three settings are 10uA, 70uA and 150uA, as
shown in Table 3.
Table 3.
IGQ Gate Current Selection
Typically, the delay from IGQ1 and IGQ0 selection to a change
in the GATE pin current is less than 1
μ
second.
Figure 11. Slew Rate (Inrush Current) Control
Gate Capacitor, Filtering and Feedback
The FET control circuit includes an FET feedback capacitor
C
2
, which provides compensation for the FET during turn on.
The capacitor value depends on the load, the choice of FET
(because of the FET internal capacitances) and the FET
gate current.
The value of C2 can be selected with the following formula.
Where:
I
GATE
= FET Gate current
I
INRUSH
= Maximum desired inrush current
C
LOAD
= DC/DC bulk capacitance
With the X80070, there is some control of the gate current
with the IGQ pins, so one selection of C2 can cover a wide
range of possible loading conditions. Typical values for C2
range from 2.2 to 4.7nF.
When power is applied to the system, the FET tries to turn on
due to its internal gate to drain capacitance (Cgd) and the
feedback capacitor C2 (see Figure 11.) The X80070 device,
when powered, pulls the gate output low to prevent the gate
voltage from rising and keep the FET from turning on. However,
unless V
DD
powers up very quickly, there will be a brief period
of time during initial application of power when the X80070
circuits cannot hold the gate low. The use of an external
capacitor (C1) prevents this. Capacitors C1 and C2 form a
voltage divider to prevent the gate voltage from rising above the
FET turn on threshold before the X80070 can hold the gate low.
Use the following formula for choosing C1.
Where:
V1 = Maximum input voltage,
V2 = FET threshold Voltage,
C1 = Gate capacitor,
C2 = Feedback capacitor.
In a system where V
DD
rises very fast, a smaller value of C1
may suffice as the X80070 will control voltage at the gate
before the voltage can rise to the FET turn on threshold. The
circuit of Figure 11 assumes that the input voltage can rise to
80V before the X80070 sees operational voltage on V
DD
. If C1
is used then the series resistor R1 will be required to revent
high frequency oscillations.
Power Good Indication
The PWRGD signal asserts (Logic LOW) only when all of the
below conditions are true:
– there is no overvoltage or no undervoltage condition, (i.e.
undervoltage < V
EE
< overvoltage.)
– There is no overcurrent condition (i.e. V
EE
- V
SENSE
<
V
OC
.)
– The FET is turned on (i.e. V
GATE
> V
DD
- 1V)
IGQ1
pin
0
0
1
1
IGQ0
pin
0
1
0
1
Operation
Defaults to gate current 50
μ
A
Gate Current is 10
μ
A
Gate Current is 70
μ
A
Gate Current is 150
μ
A
SENSE
V
EE
R
SENSE
LOAD
RDS
ON
V DD
i.e. 12V
50μA
Slew Rate
Logic
GATE
I
INRUSH
Gate
Current
Select
Logic
IGQ1
IGQ0
-48V
100
100n
22K
3.3nF
C1
C2
R2
R1
C2
I
----------I
C
×
INRUSH
=
C1
V1
V2
–
V2
=
X80070, X80071, X80072, X80073
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