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參數(shù)資料
| 型號(hào)： | X80001 |
| 廠商： | Intersil Corporation |
| 英文描述： | Smart Power Plug Penta-Power Sequence Controller with Hot Swap |
| 中文描述： | 智能電源插頭五-序控制器電源熱插拔 |
| 文件頁數(shù)： | 5/37頁 |
| 文件大?。?/td> | 695K |
| 代理商： | X80001 |
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5
FN8148.0
March 18, 2005
Equivalent A.C. Output Load Circuit
t
MRHD
Delay from MRH disable to GATE reaching 1V
I
GATE
= 60μA, No Load
1.8
2.6
μ
s
t
RESET_E
Delay from PWRGD or ViGOOD to RESET valid
LOW
1
μ
s
t
QC
Delay from IGQ1 and IGQ0 to valid Gate pin
current
1
μ
s
t
SC_RETRY
Delay between retries
TSC1 = 0; TSC0 = 0
90
100
110
ms
t
NF
Noise Filter for Overcurrent
TF1 = 0; TF0 = 1
4.5
5
5.5
μs
t
DPOR
Device Delay before Gate assertion
45
50
55
ms
t
SPOR
Delay after PWRGD and all ViGOOD signals are
active before RESET assertion
TPOR1 = 0; TPOR0 = 0
90
100
110
ms
t
TO
ViGOOD turn off time
50
ns
t
PDHLPG
(Note 1)
Delay from Drain good to PWRGD LOW
Gate = V
DD
1
μ
s
t
PDLHPG
(Note 1)
Delay from Drain fail to PWRGD HIGH
Gate = V
DD
1
μ
s
t
PGHLPG
(Note 1)
Delay from Gate good to PWRGD LOW
Drain = V
EE
1
μ
s
t
PGLHPG
(Note 1)
Delay from Gate fail to PWRGD HIGH
Drain = V
EE
1
μ
s
NOTE:
1. This parameter is based on characterization data.
Electrical Specifications
Standard Settings
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A.C. Test Conditions
Input pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing levels
V
CC
x 0.5
Output load
Standard output load
5V
SDA
30pF
4.6k
RESET
FAR
PWRGD
30pF
V1GOOD,
5V
4.6k
30pF
V2GOOD,
V3GOOD,
V4GOOD,
5V
4.6k
X80000, X80001
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