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參數(shù)資料
| 型號： | X80001 |
| 廠商： | Intersil Corporation |
| 英文描述： | Smart Power Plug Penta-Power Sequence Controller with Hot Swap |
| 中文描述： | 智能電源插頭五-序控制器電源熱插拔 |
| 文件頁數(shù)： | 20/37頁 |
| 文件大小： | 695K |
| 代理商： | X80001 |
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20
FN8148.0
March 18, 2005
When exceeding the overcurrent retry limit, the status bit
“FAR_STAT” is set to ‘1’ and the FAR pin is asserted. To
clear FAR_STAT, write to the control register. Refer to
instructions on writing to the FDR (See Table 9).
Gate Drive Output Slew Rate (Inrush Current)
Control
The gate output drives an external N-Channel FET. The
GATE pin goes high when no overcurrent, undervoltage or
overvoltage conditions exist.
The X80000 provides an I
GATE
current of 50μA to provide
on-chip slew rate control to minimize inrush current. This
current is programmable from 10μA to 160uA (in 10μA
steps) to allow the X80000 to support various load conditions
(See Figure 23 and Figure 28). I
GATE
is chosen to limit the
inrush current and to provide the best charge time for a
given load, while avoiding overcurrent conditions. The user
programs the I
GATE
current using four I
GATE
control bits.
For applications that require different ramp rates during
insertion and start-up and operations modes, the X80000
provides two external pins, IGQ1 and IGQ0, that allow the
user to switch to different GATE currents on-the-fly by
selecting one of four pre-selected I
GATE
currents. When
IGQ0 and IGQ1 are left unconnected, the gate current is
determined by the gate control bits. The other three settings
are 10μA, 70μA and 150μA. Typically, the delay from IGQ1
and IGQ0 selection to a change in the GATE pin current is
less than 1
μ
second.
Programmable Slew Rate (Gate) Control
As shown in Figure 29, this circuit block contains a
selectable current source (I
GATE
) that drives the 50μA
current into the GATE pin. This current provides a controlled
slew rate for the FET.
X80000 allows the user to change the gate current to one of
sixteen possible I
GATE
values. The options allow currents of
between 10
μ
A to 160
μ
A in 10
μ
A increments.
Once the overcurrent condition and the amount of load is
known, an appropriate slew rate can be determined and
selected for the external FET. This will ensure proper
TABLE 6. RETRY AND EVENT SEQUENCE OPTIONS
NR2 NR1 NR0
N
RETRY
AND RETRY SEQUENCE OF EVENTS
(FAILURE MODE)
0
0
0
Always Retry, Do Not assert FAR pin (Default)
0
0
1
N
RETRY
= 1 (one retry), assert FAR pin after
N
RETRY,
STOP retry, and shutoff GATE pin
0
1
0
N
RETRY
= 2 (two retries), assert FAR pin after
N
RETRY,
STOP retry, and shutoff GATE pin
0
1
1
N
RETRY
= 3 (three retries), assert FAR pin after
N
RETRY,
STOP retry, and shutoff GATE pin
1
0
0
N
RETRY
= 4 (four retries), assert FAR pin after
N
RETRY,
STOP retry, and shutoff GATE pin
1
0
1
N
RETRY
= 5 (five retries), assert FAR pin after
N
RETRY,
STOP retry, and shutoff GATE pin
1
1
0
Always Retry, assert FAR pin after 1st retry; clear
FAR when FOC cleared, do not shutoff GATE
pin.
1
1
1
N
RETRY
= 0 (no retry), asset FAR, and shutoff
GATE pin.
TABLE 7. RETRY EVENT DELAY OPTIONS
TSC1
TSC0
t
SC_RETRY
,
DELAY BETWEEN RETRIES
0
0
100 miliseconds
0
1
500 miliseconds
1
0
1 second
1
1
5 seconds
TABLE 8. OVERCURRENT FLAG BIT
STATUS
BIT
VIOLATION (ON)
NORMAL (OFF)
FOC
FOC = 0, when
V
RSENSE
> V
OC
FOC = 1, when:
V
RSENSE
< V
OC
- 0.2V
and reset by a write operation
or hardshort retry is initiated.
TABLE 9. RETRY COUNT FAILURE STATUS BIT
STATUS BIT
CONDITION
FAR_STAT
if FAR_STAT = 1, FAR is asserted.
if FAR_STAT = 0, FAR is deasserted
I
Overcurrent
I
GATE
I
GATE
= 60μA
100μA
75μA
25μA
10μA
T1
TIME (ms)
T2
T3
T4
T5
FIGURE 28. SELECTING I
GATE
CURRENT FOR SLEW RATE
CONTROL ON THE GATE PIN
X80000, X80001
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