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參數(shù)資料
| 型號： | X79002V20I |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | NV DAC with Selectable Output Range and Memory |
| 中文描述： | SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 270K |
| 代理商： | X79002V20I |
6
FN8147.0
March 17, 2005
Notes: 1. INL, DNL, Offset Error and Full Scale error measured at Vbuf with VFB connected to Vbuf.
2. The V
L
and V
H
levels are set using the configuration register according to the following table:
Address
VH2
VH1
3Ch
1
0
This setting corresponds to the nominal values of V
H
= 3.025V and V
L
= 0.151V
3. INL is measured at the maximum range of (V
H
-V
L
). INL varies inversely with the range of (V
H
-V
L
). DNL increases at lower
(V
H
-V
L
) ranges but the DAC retains montonicity.
4. Total offset error scales with V
L
according to (1% x V
L
) + 10mV and total full scale error scales with V
H
according to (1% x V
H
) + 10mV
5. Guaranteed by characterization, not 100% tested.
6. f
SCK
= 5MHz, using SPI interface test conditions on pg. 8.
ENDURANCE AND DATA RETENTION
(V
CC
= 5V ±10%, T
A
= Full Operating Temprature Range)
SYMBOL TABLE
V
POR
V
RDY
T
RDY
Power-on reset threshold voltage
RDY indicator minimum voltage
RDY indicator delay
1.5
2.6
100
2.8
2.8
6000
V
V
μs
See figure 1.
2k
and 100pF between Vcc and
RDY
(4)
VH0
1
VL2
0
VL1
0
VL0
1
Count 8
X
Count 10
X
X = don’t care
Parameter
Minimum endurance
Data retention
100,000
10
Data changes per bit
Years
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions / Notes
FIGURE 1. RDY PIN TIMING
V
RDY
V
(RDY)
0V
T
RDY
Device
Ready
Power-down
Device Disabled
V
CC
Time
Time
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
May change
from High to
Low
Will change
from Low to
High
Will change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
V
OUT
OE
t
OEDIS
t
OEVALID
V
buf = High Impedance
Vbuf OUTPUT ENABLE TIMING
X79000, X79001, X79002
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