參數(shù)資料
型號： X79002V20I
廠商： INTERSIL CORP
元件分類： DAC
英文描述： NV DAC with Selectable Output Range and Memory
中文描述： SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PDSO20
封裝： PLASTIC, TSSOP-20
文件頁數(shù)： 4/18頁
文件大小： 270K
代理商： X79002V20I
4
FN8147.0
March 17, 2005
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to Vss
Temperature under bias........................ -40°C to 85°C
Storage temperature .........................-65°C to +150°C
Voltage on every pin except Vcc ............. -0.5V to +7V
Voltage on Vcc Pin.....................................-0.5V to 6V
D.C. Output Current at pins SO and RDY............5 mA
D.C. Output Current at pins VL, VH,
VFB, Vout and Vref .............................-0.50 to 1 mA
VBUF output short circuit duration.............10 seconds
Lead temperature (soldering, 10 seconds)........ 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or an other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, all typical values are for 25°C ambient temperature and 5V at pin Vcc. Maximum and minimum
specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin Vss. All bits in
control registers are “0”. SPI interface in “standby” (see notes 1 and 2 on page 6). Output pins unloaded. Input pins floating.
DAC input is 000hex.)
Parameter
Min.
-40
4.5
-0.3
Max.
+85
5.5
Vcc +0.3
Units
°C
V
V
Temperature
Voltage on Vcc Pin
Voltage on any other Pin
Parameter
Min
Typ
Max
Units
Notes
Buffered DAC and Reference
Resolution
INL
DNL
Total Offset Error
Total Fullscale Error
Total Offset Error Drift
Total Fullscale Error Drift
Settling time to 1 LSB
12
bit
LSB
LSB
mV
mV
ppm/°C
ppm/°C
μs
μs
±10
0.5
12
22
(1)(2)(3)
VL = 0.151V, VH = 3.025V
-0.5
(1)(2)(4)
VL = 0.151V, VH = 3.025V
50
50
2
6
(1)(2)(4)
VL = 0.151V, VH = 3.025V
10
30
Step size
≤
100mV
(2)(5)
Step size up to full scale
(2)(5)
Buffer Only
Output Buffer Offset
Output Buffer Offset Drift
DC PSRR
Vbuf output slew rate
Output Buffer 3dB Bandwidth
-6
-20
-1.5
0.2
300
6
mV
μV/°C
mV/V
V/μs
kHz
150mV < Vout < V
CC
- 150mV
(5)
20
+1.5
(5)
1000
150mV < (V(VFB) =
V(Vbuf)) < V
CC
– 150mV
(5)
(6)
Digital feed through
Output load regulation
10
nVsec
mV/mA
-1
1
140mV
≤
V(Vbuf)
≤
V
CC
-140mV
I(Vbuf) = ±1mA
V(Vbuf) = V
CC
or 0V
Rload
≥
2k
(5)
Short circuit current @ Vbuf
Capacitive Loading Stability
50
mA
pF
100
X79000, X79001, X79002
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