參數(shù)資料
型號(hào): X4C105
元件分類: CPU監(jiān)測
英文描述: RTC Module With CPU Supervisor
中文描述: 時(shí)鐘模塊CPU監(jiān)控
文件頁數(shù): 7/18頁
文件大小: 93K
代理商: X4C105
X4C105
7
Acknowledge Polling
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indicate
the end of the master’s byte load operation, the device
initiates the internal non volatile write cycle. Acknowledge
polling can be initiated immediately. To do this, the
master issues a start condition followed by the Slave
Address Byte for a write or read operation. If the device is
still busy with the high voltage cycle then no ACK will be
returned. If the device has completed the write operation,
an ACK will be returned and the host can then proceed
with the read or write operation. Refer to the flow chart in
Figure 8.
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of the
Slave Address Byte is set to one. There are three basic
read operations: Current Address Read, Random Read,
and Sequential Read.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address
n+1. On power up, the address of the address counter is
undefined, requiring a read or write operation for
initialization.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to figure 9 for the address,
acknowledge, and data transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Random Read
A Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation. The
master issues the start condition and the Slave Address
Byte, receives an acknowledge, then issues the Word
Address Byte. After acknowledging receipts of the Word
Address Byte, the master immediately issues another
start condition and the Slave Address Byte with the R/W
bit set to one. This is followed by an acknowledge from
the device and then by the eight bit word. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition. Refer to
figure 10 for the address, acknowledge, and data transfer
sequence.
ACK
returned
Issue Slave Address
Byte (Read or Write)
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
High Voltage Cycle
complete. Continue
command sequence
Issue STOP
NO
Continue normal
Read or Write
command sequence
PROCEED
YES
Figure 8. Acknowledge Polling Sequence
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