參數(shù)資料
型號: X40430
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述: 雙電壓監(jiān)視器集成CPU監(jiān)控
文件頁數(shù): 6/26頁
文件大?。?/td> 142K
代理商: X40430
X40430/X40431/X40434/X40435 – Preliminary
Characteristics subject to change without notice.
6 of 26
REV 1.3.16 7/13/02
www.xicor.com
C
ASE
A
Now if the desired V
TRIPX
is greater than the V
TRIPX
(actual), then add the difference between V
TRIPX
(desired) – V
TRIPX
(actual) to the original V
TRIPX
desired. This is your new V
TRIPX
that should be applied
to VXMON and the whole sequence should be
repeated again (see Figure 5).
C
ASE
B
Now if the V
TRIPX
(actual), is higher than the V
TRIPX
(desired), perform the reset sequence as described in
the next section. The new V
TRIPX
voltage to be applied
to VXMON will now be: V
TRIPX
(desired) – (V
TRIPX
(actual) – V
TRIPX
(desired)).
Note:
This operation does not corrupt the memory array.
Setting a Lower V
TRIPx
Voltage (x=1, 2, 3)
In order to set V
TRIPx
to a lower voltage than the
present value, then V
TRIPx
must first be “reset” accord-
ing to the procedure described below. Once V
TRIPx
has been “reset”, then V
TRIPx
can be set to the desired
voltage using the procedure described in “Setting a
Higher V
TRIPx
Voltage”.
Resetting the V
TRIPx
Voltage
To reset a V
TRIPx
voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
TRIP1
, 0Bh for V
TRIP2
, and 0Fh for V
TRIP3
, followed
by 00h for the Data Byte in order to reset V
TRIPx
. The
STOP bit following a valid write operation initiates the
programming sequence. Pin WDO must then be
brought LOW to complete the operation.
After being reset, the value of V
TRIPx
becomes a nomi-
nal value of 1.7V or lesser.
Notes:
1. This operation does not corrupt the memory array.
2. Set V
CC
1.5(V2MON or V3MON), when setting
V
TRIP2
or V
TRIP3
respectively.
CONTROL REGISTER
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed with a special pre-
amble in the slave byte (1011) and is located at
address 1FFh. It can only be modified by performing a
byte write operation directly to the address of the regis-
ter and only one data byte is allowed for each register
write operation. Prior to writing to the Control Register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Registers" on page 7.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, and BP. The X40430/31/34/
35 will not acknowledge any data bytes written after
the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 1FFh,
using the special preamble. Only one byte is read by
each register read operation. The master should
supply a stop condition to be consistent with the bus
protocol.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
7
6
5
4
3
0
2
1
0
PUP1 WD1
WD0
BP
RWEL WEL PUP0
Figure 5. Sample V
TRIP
Reset Circuit
1
6
2
7
14
13
9
8
X4043X
V
TRIP1
Adj.
V
P
SDA
SCL
μC
Adjust
Run
V2FAIL
V
TRIP2
Adj.
RESET
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