參數(shù)資料
型號(hào): X40430
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述: 雙電壓監(jiān)視器集成CPU監(jiān)控
文件頁(yè)數(shù): 3/26頁(yè)
文件大?。?/td> 142K
代理商: X40430
X40430/X40431/X40434/X40435 – Preliminary
Characteristics subject to change without notice.
3 of 26
REV 1.3.16 7/13/02
www.xicor.com
6
RESET/
RESET
RESET Output.
V
CC
falls below V
grammed time period (t
for t
PURST
thereafter.
RESET Output.
falls below V
time period (t
thereafter.
Ground
Serial Data.
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a
pull up resistor and the input buffer is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and
followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the
watchdog time out period results in WDO going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH prevents writes to any location in the device (including all the registers). It has
an internal pull down resistor (>10M
typical).
V3 Voltage Monitor Input.
When the V3MON input is less than the V
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
third power supply with no external components. Connect V3MON to V
V3MON comparator is supplied by the V3MON input.
V3 Voltage Fail Output.
This open drain output goes LOW when V3MON is less than V
HIGH when V3MON exceeds V
TRIP3
. There is no power up reset delay circuitry on this pin.
WDO Output.
WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
Supply Voltage
(X40431/35) This open drain pin is an active LOW output which goes LOW whenever
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
PURST
) on power up. It will also stay active until manual reset is released and
(X40430/34) This pin is an active HIGH CMOS output which goes HIGH whenever V
TRIP1
voltage or if manual reset is asserted. This output stays active for the programmed
PURST
) on power up. It will also stay active until manual reset is released and for t
CC
PURST
7
8
V
SDA
SS
SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
9
10
SCL
WP
11
V3MON
TRIP3
voltage, V3FAIL goes LOW.
SS
or
V
CC
when not used. The
12
V3FAIL
TRIP3
and goes
13
WDO
14
V
CC
PIN DESCRIPTION
(Continued)
Pin
Name
Function
PRINCIPLES OF OPERATION
Power On Reset
Applying power to the X40430/31/34/35 activates a
Power On Reset Circuit that pulls the RESET/RESET
pins active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
CC
exceeds the device V
for t
PURST
(selectable) the circuit releases the RESET
(X40431/35) and RESET (X40430/34) pin allowing the
system to begin operation.
TRIP1
threshold value
Figure 1. Connecting a Manual Reset Push-Button
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains HIGH/LOW
until the push-button is released and for t
after.
PURST
there-
V
CC
MR
System
Reset
Manual
Reset
X40430/34
RESET
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