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參數(shù)資料
| 型號(hào)： | X40420V14IZ-B |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 電源管理 |
| 英文描述： | Dual Voltage Monitor with Intergrated CPU Supervisor |
| 中文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-14 |
| 文件頁(yè)數(shù)： | 7/25頁(yè) |
| 文件大?。?/td> | 395K |
| 代理商： | X40420V14IZ-B |
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7
May 25, 2006
Resetting the V
TRIPx
Voltage
To reset a V
TRIPx
voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is set
up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
TRIP1
and 0Bh for V
TRIP2
, followed by 00h for the Data
Byte in order to reset V
TRIPx
. The STOP bit following a
valid write operation initiates the programming sequence.
Pin WDO must then be brought LOW to complete the
operation.
After being reset, the value of V
TRIPx
becomes a nominal
value of 1.7V or lesser.
Note:
This operation does not corrupt the memory array.
System Battery Switch
As long as V
CC
exceeds the low voltage detect threshold
V
TRIP
, V
OUT
is connected to V
CC
through a 5
(typical)
switch. When the V
CC
has fallen below V1
TRIP
, then V
CC
is applied to V
OUT
if V
CC
is or equal to or greater than
V
BATT
- 0.03V. When V
CC
drops to less than V
BATT
-
0.03V, then V
OUT
is connected to V
BATT
through an 80
(typical) switch. V
OUT
typically supplies the system static
RAM voltage, so the switchover circuit operates to pro-
tect the contents of the static RAM during a power failure.
Typically, when V
CC
has failed, the SRAMs go into a
lower power state and draw much less current than in
their active mode. When V
CC
returns, V
OUT
switches
back to V
CC
when V
CC
exceeds V
BATT
+ 0.03V. There is
a 60mV hysteresis around this battery switch threshold to
prevent oscillations between supplies.
While V
CC
is connected to V
OUT
the BATT-ON pin is
pulled LOW. The signal can drive an external PNP tran-
sistor to provide additional current to the external circuits
during normal operation.
Operation
The device is in normal operation with V
CC
as long as
V
CC
> V
TRIP1
. It switches to the battery backup mode
when V
CC
goes away.
Control Register
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The Control Register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Registers" on page 9.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, and BP. The X40420 will not
acknowledge any data bytes written after the first byte
is entered.
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condi-
tion to be consistent with the bus protocol, but a stop is
not required to end this operation.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 5. Sample V
TRIP
Reset Circuit
Condition
V
CC
> V
TRIP1
V
CC
> V
TRIP1
&
V
BATT
= 0
0
≤
V
CC
≤
V
TRIP1
and V
CC
< V
BATT
Mode of Operation
Normal Operation
Normal Operation without battery
backup capability
Battery Backup mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
7
6
5
4
3
2
1
0
PUP1 WD1
WD0
BP
0
RWEL WEL PUP0
1
6
2
7
14
13
9
8
X40420
V
TRIP1
Adj.
V
P
RESET
4.7K
SDA
SCL
μC
Adjust
Run
V2FAIL
V
TRIP2
Adj.
X40420, X40421
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X40420S14IZ-A | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40420S14IZ-B | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40420S14Z-A | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40420S14Z-B | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40420V14IZ-A | Dual Voltage Monitor with Intergrated CPU Supervisor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X40420V14Z-A | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch |
| X40420V14Z-B | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch |
| X40421 | 制造商:XICOR 制造商全稱(chēng):Xicor Inc. 功能描述:Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch |
| X40421EVAL | 制造商:Intersil Corporation 功能描述:X40421 EVALUATION KIT - Bulk |
| X40421S14-A | 功能描述:IC VOLT MON DUAL SUP/SW 14-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類(lèi)型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
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