參數(shù)資料
型號(hào): X40420V14IZ-B
廠(chǎng)商: INTERSIL CORP
元件分類(lèi): 電源管理
英文描述: Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述: 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝: 4.40 MM, ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-14
文件頁(yè)數(shù): 3/25頁(yè)
文件大小: 395K
代理商: X40420V14IZ-B
3
May 25, 2006
Low V
CC
detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when V
CC
falls below the minimum V
TRIP1
point.
RESET/RESET is active until V
CC
returns to proper
operating level and stabilizes. A second voltage moni-
tor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Intersil’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
A battery switch circuit compares V
CC
with V
BATT
input
and connects V
OUT
to whichever is higher. This pro-
vides voltage to external SRAM or other circuits in the
event of main power failure. The X40420, X40421 can
drive 50mA from V
CC
to 250μA from V
BATT
. The
device only switches to V
BATT
when V
CC
drops below
the low V
CC
voltage threshold and V
BATT
.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as x 8. The device
features an 2-wire interface and software protocol
allowing operation on a two-wire bus.
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
Example Application
Unreg.
Supply
5V
REG
+
Manual
Reset
Enable
SRAM
Addr
Addr
NMI
IRQ
RESET
I
2
C
uC
V
CC
BATT-ON
V
CC
V
BATT
V
OUT
V2MON
V2FAIL
VDO
RESET
MR
SCL SDA
X40420, X40421
V
BATT
WP
V
SS
V
CC
BATT-ON
SDA
SCL
3
4
5
2
1
12
11
10
13
14
LOWLINE
WDO
RESET
7
6
8
9
V2MON
MR
3
4
5
2
1
12
11
10
13
14
7
6
8
9
V
OUT
V2FAIL
V
BATT
WP
V
CC
BATT-ON
SDA
SCL
V
OUT
V
SS
LOWLINE
WDO
RESET
V2MON
MR
V2FAIL
X40420
X40421
14-Pin SOIC, TSSOP
14-Pin SOIC, TSSOP
PIN DESCRIPTION
Pin
1
Name
V2FAIL
Function
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and
goes HIGH when V2MON exceeds V
TRIP2
. There is no power-up reset delay circuitry on this pin.
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
SS
or
V
CC
when
not used.
Early Low V
CC
Detect.
This open drain output signal goes LOW when
V
CC
< V
TRIP1
.
When
V
CC
> V
TRIP1
, this pin is pulled high with the use of an external pull up resistor.
WDO Output.
WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
Manual Reset Input.
Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain
HIGH/LOW until the pin is released and for the t
PURST
thereafter. It has an internal pull up resistor.
2
V2MON
3
LOWLINE
4
WDO
5
MR
X40420, X40421
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