參數(shù)資料
型號(hào)： X40239
英文描述： Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP(帶2K EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器)
中文描述： 綜合系統(tǒng)管理IC三電壓監(jiān)測(cè)器，葡萄牙，2千比特的EEPROM內(nèi)存，單/雙副處長(zhǎng)（帶2K的EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器）
文件頁(yè)數(shù)： 20/39頁(yè)
文件大?。?/td> 215K
代理商： X40239
X4023x
– Preliminary Information
Characteristics subject to change without notice.
20 of 39
REV 1.0.4 7/12/01
www.xicor.com
CR Register Write Operation
The CR register is accessed using the Slave Address
set to 1010010 (Refer to Figure 4). Following the Slave
Address Byte, access to the CR register requires an
Address Byte which must be set to FFh. Only one data
byte is allowed to be written for each CR register Write
operation. The user must issue a STOP, after sending
this byte to the register, to initiate the nonvolatile cycle
that stores the BP1, BP0, PUP1 and PUP0 bits. The
X4023x will not ACKNOWLEDGE any data bytes writ-
ten after the first byte is entered (Refer to Figure 18).
Prior to writing to the CR register, the WEL and RWEL
bits must be set using a two step process, with the
whole sequence requiring 3 steps
—Write a 02H to the CR Register to set the Write Enable
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a START
and ended with a STOP).
—Write a 06H to the CR Register to set the Register
Write Enable Latch (RWEL) AND the WEL bit. This is
also a volatile cycle. The zeros in the data byte are
required. (Operation preceded by a START and ended
with a STOP).
—Write a one byte value to the CR Register that has all
the bits set to the desired state. The CR register can be
represented as qxyst01r in binary, where xy are the
Voltage Monitor Output Status (V2FS and V3FS) bits, st
are the Block Lock Protection (BL1 and BL0) bits, and
qr are the Power On Reset delay time (t
bits (PUP1 - PUP0). This operation is proceeded by a
START and ended with a STOP bit. Since this is a non-
volatile write cycle, it will typically take 5ms to complete.
The RWEL bit is reset by this cycle and the sequence
must be repeated to change the nonvolatile bits again.
If bit 2 is set to ‘1’ in this third step (qxys t11r) then the
RWEL bit is set, but the V2FS, V3FS, PUP1, PUP0,
BL1 and BL0 bits remain unchanged. Writing a second
byte to the control register is not allowed. Doing so
aborts the write operation and the X4023x does not
return an ACKNOWLEDGE.
PURST
) control
For example, a sequence of writes to the device CR
register consisting of [02H, 06H, 02H] will reset all of
the nonvolatile bits in the CR Register to “0”.
It should be noted that a write to any nonvolatile bit of
CR register will be ignored if the Write Protect pin of the
X4023x is active (HIGH) (See "WP: Write Protection
Pin").
CR (Control) Register Read Operation
The contents of the CR Register can be read at any
time by performing a random read (See Figure 18).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each
register read operation. The X4023x resets itself after
the first byte is read. The master should supply a STOP
condition to be consistent with the bus protocol.
After setting the WEL and / or the RWEL bit(s) to a “1”,
a CR register read operation may o
rupting a proceeding CR register write operation.
CC
ur, without inter-
DATA PROTECTION
There are a number of levels of data protection fea-
tures designed into the X4023x. Any write to the device
first requires setting of the WEL bit in the CR register. A
write to the CR register itself, further requires the set-
ting of the RWEL bit. Block Lock protection of the
device enables the user to inhibit writes to certain
regions of the EEPROM memory, as well as to all the
DCPs. One further level of data protection in the
X4023x, is incorporated in the form of the Write Protec-
tion pin.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X4023x.
The table below (X4023x Write Permission Status)
summarizes the effect of the WP pin (and Block Lock),
on the write permission status of the device.
Additional Data Protection Features
In addition to the preceding features, the X4023x also
incorporates the following data protection functionality:
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol-
atile write cycle.
VOLTAGE MONITORING FUNCTIONS
V
The X4023x monitors the supply voltage and drives the
RESET output HIGH (using an external “pull up” resis-
tor) if V
CC
is lower than V
TRIP1
output will remain HIGH until V
minimum time of t
PURST
. After this time, the RESET
pin is driven to a LOW state. See Figure 30.
CC
Monitoring
threshold. The RESET
exceeds V
CC
TRIP1
for a
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