參數(shù)資料
型號(hào): X40235
廠商: Intersil Corporation
英文描述: Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
中文描述: 三電壓監(jiān)測(cè)器,葡萄牙,2千比特EEPROM存儲(chǔ)器,以及單/雙副處長(zhǎng)
文件頁數(shù): 18/36頁
文件大?。?/td> 541K
代理商: X40235
18
FN8115.0
April 11, 2005
CONTROL AND STATUS REGISTER
The Control and Status (CR) Register provides the user
with a mechanism for changing and reading the status
of various parameters of the X4023x (See Figure 17).
The CR register is a combination of both volatile and
nonvolatile bits. The nonvolatile bits of the CR register
retain their stored values even when V
CC
is powered
down, then powered back up. The volatile bits how-
ever, will always power-up to a known logic state “0”
(irrespective of their value at power-down).
A detailed description of the function of each of the CR
register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the
entire X4023x device. This bit must first be enabled
before ANY write operation (to DCPs, EEPROM mem-
ory array, or the CR register). If the WEL bit is not first
enabled, then ANY proceeding (volatile or nonvolatile)
write operation to DCPs, EEPROM array, as well as
the CR register, is aborted and no ACKNOWLEDGE is
issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the
disabled, LOW (0) state. The WEL bit is enabled / set
by writing 00000010 to the CR register. Once enabled,
the WEL bit remains set to “1” until either it is reset to
“0” (by writing 00000000 to the CR register) or until the
X4023x powers down, and then up again.
Writes to the WEL bit do not cause an internal high
voltage write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition
is executed in the CR Write command sequence (See
Figure 18).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CR) Register Write Enable
status of the X4023x. Therefore, in order to write to
any of the bits of the CR Register (except WEL), the
RWEL bit must first be set to “1”. The RWEL bit is a
volatile bit that powers up in the disabled, LOW (“0”)
state.
It must be noted that the RWEL bit can only be set,
once the WEL bit has first been enabled (See "CR
Register Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of three cases:
—After a successful write operation to any bits of the CR
register has been completed (See Figure 18).
—When the X4023x is powered down.
—When attempting to write to a Block Lock protected
region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).
BL1, BL0: Block Lock protection bits - (Nonvolatile)
The Block Lock protection bits (BL1 and BL0) are used
to:
—Inhibit a write operation from being performed to cer-
tain addresses of the EEPROM memory array
—Inhibit a DCP write operation (changing the “wiper
position”).
The region of EEPROM memory which is protected /
locked is determined by the combination of the BL1
and BL0 bits written to the CR register. It is possible to
lock the regions of EEPROM memory shown in the
table below:
If the user attempts to perform a write operation on a
protected region of EEPROM memory, the operation
is aborted without changing any data in the array.
Bit(s)
WEL
RWEL
V2FS
V3FS
BL1 - BL0
PUP1 - PUP0
Description
Write Enable Latch bit
Register Write Enable Latch bit
V2MON Output Flag Status
V3MON Output Flag Status
Sets the Block Lock partition
Sets the Power-on Reset time
PUP1
WEL
PUP0
CS5
CS6
CS7
CS4
CS3
CS2
CS1
CS0
V3FS
V2FS
BL0
BL1
RWEL
Figure 17. CR Register Format
NV
NV
NV
NV
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
BL1
0
BL0
0
Protected Addresses
(Size)
None (Default)
C0
h
- FF
h
(64 bytes
)
80
h
- FF
h
(128 bytes
)
00
h
- FF
h
(256 bytes)
Partition of array
locked
None (Default)
0
1
Upper 1/4
1
0
Upper 1/2
1
1
All
X40231, X40233, X40235, X40237, X40239
相關(guān)PDF資料
PDF描述
X40237 Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
X40239 Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
X40420V14IZ-B Dual Voltage Monitor with Intergrated CPU Supervisor
X40420S14IZ-A Dual Voltage Monitor with Intergrated CPU Supervisor
X40420S14IZ-B Dual Voltage Monitor with Intergrated CPU Supervisor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
X40235S16I-A 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40235S16I-AT1 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40235S16I-B 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40235S16I-BT1 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40237 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP