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參數(shù)資料
| 型號(hào)： | X24645G |
| 廠商： | IC MICROSYSTEMS Sdn. Bhd. |
| 英文描述： | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| 中文描述： | 先進(jìn)的2線串行E2PROM與保護(hù)塊LockTM |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 331K |
| 代理商： | X24645G |
X24645
7
Figure 7. Current Address Read
Figure 8. Random Read
READ OPERATIONS
Read operations are initiated in the same manner as write
operations with the exception that the R/
W
bit of
the slave address is set HIGH. There are three basic read
operations: current address read, random read
and sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
Current Address Read
Internally the X24645 contains an address counter that
maintains the address of the last byte read, increment-
ed by one or the exact address of the last byte written.
Therefore, if the last access read was to address n, the
next read operation would access data from address
n + 1. Upon receipt of the slave address with the R/W
set HIGH, the X24645 issues an acknowledge
and transmits the byte. The read operation is terminated by
the master; by not responding with an acknowledge
and by issuing a stop condition. Refer to Figure 7 for the
sequence of address, acknowledge and data transfer.
Random Read
Random read operations allow the master to access any
memory location in a random manner. Prior to issuing
the slave address with the R/W bit set HIGH, the master must
first perform a “dummy” write operation.
The master issues the start condition, and the slave ad-
dress with the R/W bit set LOW, followed by the byte
address it is to read. After the word address acknowledge,
the master immediately reissues the start condition
and the slave address with the R/W bit set HIGH.
This will be followed by an acknowledge from the
X24645 and then by the data byte. The read operation is
terminated by the master; by not responding with an
acknowledge and by issuing a stop condition. Refer to
Figure 8 for the address, acknowledge and data
transfer sequence.
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24645
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
DATA
2783 ILL F11
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24645
S
T
A
R
T
SLAVE
ADDRESS
S
A
C
K
2783 ILL F12.1
S
T
A
R
T
S
BYTE
ADDRESS n
A
C
K
SLAVE
ADDRESS
DATA n
A
C
K
S
T
O
P
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24645GG | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GP | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GS | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GV | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645I | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24645GG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GP | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GS | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GV | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645I | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
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