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參數(shù)資料
| 型號(hào)： | X24645G |
| 廠商： | IC MICROSYSTEMS Sdn. Bhd. |
| 英文描述： | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| 中文描述： | 先進(jìn)的2線串行E2PROM與保護(hù)塊LockTM |
| 文件頁數(shù)： | 5/18頁 |
| 文件大小： | 331K |
| 代理商： | X24645G |
X24645
5
Figure 5. Byte Write
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24645
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
BYTE
ADDRESS
DATA
2783 ILL F08.1
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next two bits are the device select bits. A system could have
up to four X24645’s on the bus. The four
addresses are defined by the state of the S
1
and S
2
inputs.
S
2
of the slave address must be the inverse of
the S
2
input pin.
Figure 4. Slave Address
The next five bits of the slave address are an extension of
the array’s address and are concatenated with
the eight bits of address in the byte address field,
providing direct access to the whole 8192 x 8 array.
2783 ILL F07.1
S2
A9
A8
R/W
DEVICE
SELECT
S1
A12
HIGH ORDER
ADDRESS
BITS
A11 A10
The last bit of the slave address defines the operation to be
performed. When set HIGH a read operation is
selected, when set LOW, a write operation is selected.
Following the start condition, the X24645 monitors the SDA
bus comparing the slave address being transmitted
with its slave address device type identifier. Upon a
correct compare the X24645 outputs an acknowledge on
the SDA line. Depending on the state of the R/W bit, the
X24645 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24645 requires a second ad-
dress field. This address field is the byte address, com-
prised of eight bits, providing access to any one of 8192
words in the array. Upon receipt of the byte address, the
X24645 responds with an acknowledge and awaits the
next eight bits of data, again responding with an acknowledge
The master then terminates the transfer by generating a
stop condition, at which time the X24645 begins
the internal write cycle to the nonvolatile memory. While the
internal write cycle is in progress the X24645 inputs
are disabled, and the device will not respond to any requests
from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24645GG | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GP | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GS | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GV | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645I | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24645GG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GP | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GS | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645GV | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24645I | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
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