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參數(shù)資料
| 型號(hào)： | WHITEPAPER |
| 英文描述： | White Paper - The Mobile AMD Athlon XP Processor |
| 中文描述： | 白皮書-移動(dòng)AMD Athlon XP處理器 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 102K |
| 代理商： | WHITEPAPER |
W H I T E
P A P E
W H I T E
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The Mobile AMD Athlon XP-M Processor
March 2003
16-way set-associative 512KB L2 cache using a 72-bit (64-bit data + 8-bit ECC)
interface. The mobile AMD Athlon XP-M processor’s large integrated full-speed L1
cache is comprised of two separate 64KB, two-way set-associative data and
instruction caches which are much larger than the Pentium 4 processor’s L1 cache
(128KB vs. 8KB + 12KB
op). By featuring a larger L1 cache, applications running on
the mobile AMD Athlon XP-M processor perform exceptionally fast because more
instruction and data information is local to the processor. Applications exploit the
larger caches by benefiting from the increased support of instruction and data set
locality. The data cache also has eight banks to provide maximum parallelism for
running multiple applications. It supports concurrent accesses by two 64-bit loads or
stores. The instruction cache contains predecode data to assist multiple, high-
performance instruction decoders. Both instruction and data caches are dual-ported
and contain dedicated snoop ports designed to eliminate all system coherency traffic,
common in systems with many devices, from interfering with application
performance.
The mobile AMD Athlon XP-M processor also includes an integrated, full-
speed, 16-way set-associative, exclusive 512KB L2 cache. When the processor
requests data, it first searches the data in its L1 cache. If the processor finds the
data in its L1 cache, the result is what is known as a cache hit and the processor
retrieves the data from the low latency L1 cache. If the processor can not retrieve
the data from its L1 cache, the processor attempts to retrieve the data in its L2
cache and once again attempts to obtain a cache hit. In the event of a cache miss,
the processor must then request this data from the slower system memory. With an
additional 256KB L2 cache over previous mobile AMD Athlon XP processors, the
mobile AMD Athlon XP-M processor with 512KB L2 cache increases the performance
of applications such as high-end gaming and digital media by keeping more
frequently accessed instructions and data close to the CPU. Higher set-associativity
increases the hit rate by reducing data conflicts. This translates into more possible
locations where important data can reside in the L2 cache memory instead of system
memory. With an exclusive cache architecture, the contents of the L1 caches are not
duplicated in the L2 cache. This enables 512KB of L2 cache and 128KB of L1 cache
for a total usable storage space of 640KB.
The mobile AMD Athlon XP-M processor cache architecture also supports error
correction code (ECC) protection. With these cache architecture features, the mobile
AMD Athlon XP-M processor provides reliable, high-performance computing.
When executing software, a processor begins by decoding the program’s
instructions and translating them into operations (or Ops) that the microprocessor
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