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| 型號： | WHITEPAPER |
| 英文描述： | White Paper - The Mobile AMD Athlon XP Processor |
| 中文描述： | 白皮書-移動AMD Athlon XP處理器 |
| 文件頁數(shù)： | 16/17頁 |
| 文件大?。?/td> | 102K |
| 代理商： | WHITEPAPER |
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The Mobile AMD Athlon XP-M Processor
March 2003
Figure 1: Mobile AMD Athlon XP-M Microarchitecture Block Diagram
QuantiSpeed Architecture: Nine-issue, Superscalar,
Fully Pipelined Microarchitecture with High-Performance
Cache Memory Architecture, and Three Full x86
Instruction Decoders
At the heart of QuantiSpeed architecture is a fully pipelined, nine-issue,
superscalar processor core. The mobile AMD Athlon XP-M processor provides a wider
execution bandwidth of nine execution pipes when compared with competitive x86
processors with up to six execution pipes. The nine execution engines are comprised
of three address calculation units, three integer units, and three floating-point units.
In order to supply such a highly superscalar microarchitecture, the mobile
AMD Athlon XP-M processor implements a very large on-chip cache architecture
particularly in the L1 caches closest to the core. The mobile AMD Athlon XP-M
processor’s high-performance, on-chip cache architecture includes a dual-ported
128KB split-L1 cache with separate snoop ports, and an integrated full-speed,
Load/Store Queue Unit
IEU
AGU
Instruction Control Unit (72-entry)
Fetch/Decode
Control
2-way, 64KB Data Cache
40-entry L1 TLB/256-entry
L2 TLB
3-Way x86 Instruction Decoders
FPU Register File (88-entry)
FADD
MMX
3DNow!
FStore
FMUL
MMX
3DNow!
IEU
Integer Scheduler (18-entry)
FPU Stack Map/Rename
2-way, 64KB Instruction Cache
24-entry L1 TLB/256-entry L2 TLB
Predecode
Cache
Branch Prediction
Table
2-way, 64KB Instruction Cache
24-entry L1 TLB/256-entry L2 TLB
Predecode
Cache
Branch Prediction
Table
L2 Cache
16-way,
512KB
L2 Cache
16-way,
512KB
Bus
Interface
Unit
Bus
Interface
Unit
FPU Scheduler (36-entry)
AGU
IEU
AGU
System Interface
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