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參數(shù)資料
| 型號： | WEDPN16M72VR-100BM |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 161K |
| 代理商： | WEDPN16M72VR-100BM |
WEDPN16M72VR-XBX
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
9
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
(VCC = +3.3V ±0.3V; TA = -55°C TO +125°C)
Parameter/Condition
Symbol
Units
Min
Max
Supply Voltage
VCC
33.6
V
Input High Voltage: Logic 1; All inputs (21)
VIH
2VCC + 0.3
V
Input Low Voltage: Logic 0; All inputs (21)
VIL
-0.3
0.8
V
Input Leakage Current: Any input 0V - VIN - VCC(All other pins not under test = 0V)
II
-5
5
A
Output Leakage Current: I/Os are disabled; 0V - VOUT - VCC
IOZ
-5
5
A
Output Levels:
Output High Voltage (IOUT = -4mA)
VOH
2.4
–
V
Output Low Voltage (IOUT = 4mA)
VOL
–
0.4
V
ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
Voltage on VDD, VDDQ Supply relative to Vss
-1 to 4.6
V
Voltage on NC or I/O pins relative to Vss
-1 to 4.6
V
Operating Temperature TA (Mil)
-55 to +125
°C
Operating Temperature TA (Ind)
-40 to +85
°C
Storage Temperature, Plastic
-55 to +150
°C
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
CAPACITANCE (NOTE 2)
Parameter
Symbol
Max
Unit
Input Capacitance: CLK
CI1
20
pF
Addresses, BA0-1 Input Capacitance
CA
8
pF
InputCapacitance:Allotherinput-onlypins
CI2
10
pF
Input/Output Capacitance: I/Os
CIO
10
pF
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1,6,11,13)
(VCC = +3.3V ±0.3V; TA = -55°C TO +125°C)
Parameter/Condition
Symbol
Max
Units
Operating Current: Active Mode;
ICC1
875
mA
Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (3, 18, 19)
Standby Current: Active Mode; CKE = HIGH; CS = HIGH;
ICC3
300
mA
All banks active after tRCD met; No accesses in progress (3, 12, 19)
Operating Current: Burst Mode; Continuous burst;
ICC4
850
mA
Read or Write; All banks active; CAS latency = 3 (3, 18, 19)
Self Refresh Current: CKE - 0.2V (27, 28)
ICC7
25
mA
commands. First, CLK must be stable (stable clock is defined
as a signal cycling within timing constraints specified for the
clock pin) prior to CKE going back HIGH. Once CKE is HIGH,
the SDRAM must have NOP commands issued (a minimum of
two clocks) for tXSR, because time is required for the completion
of any internal refresh in progress.
* Self refresh available in commercial and industrial temperatures only.
Upon exiting the self refresh mode, AUTO REFRESH com-
mands must be issued as both SELF REFRESH and AUTO
REFRESH utilize the row refresh counter.
BGA THERMAL RESISTANCE
Description
Symbol
Max
Unit
Notes
Junction to Ambient (No Airflow)
Theta JA
14.1
C/W
1
Junction to Ball
Theta JB
10.2
C/W
1
Junction to Case (Top)
Theta JC
3.7
C/W
1
NOTE:
Refer to Application Note “PBGA Thermal Resistance Correlation” at
www.whiteedc.com in the application notes section for modeling conditions.
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