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參數(shù)資料
| 型號： | WED9LC6816V1612BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA153 |
| 封裝： | 14 X 22 MM, MO-163, BGA-153 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 324K |
| 代理商： | WED9LC6816V1612BC |
WED9LC6816V
16
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September, 2003
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
FIG. 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDRAS#
SDWE#
BWE#
SDCAS#
ADDR
Ra
Ca0
Cb0
Cd0
Cc0
BA0, 1
[A12,A13]
SDA10
Ra
CL=2
Qa0
Qa1
Qb0
Qb1
Qb2
Dd0
Dc0
Dc1
Dd1
tRDL
CL=3
DQ
Qa0
Qa1
Qa2
Qa3
Dd0
Dc0
Dc1
Dd1
tCDL
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
tRCD
SDCE#
Note 2
Note 3
Note 1
NOTES:
1.
To write data before burst read ends. BWE# should be asserted three cycle prior to write command to avoid bus contention.
2.
Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3.
BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be
masked internally.
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