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參數(shù)資料
| 型號： | WED9LC6816V1310BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA153 |
| 封裝： | 14 X 22 MM, MO-163, BGA-153 |
| 文件頁數(shù)： | 24/26頁 |
| 文件大?。?/td> | 324K |
| 代理商： | WED9LC6816V1310BI |
WED9LC6816V
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September, 2003
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
(Vcc = 3.3V -5% / +10% unless otherwise noted; 0°CtA70°C, Commercial; -40°CtA85°C, Industrial)
NOTES:
1.
Parameters depend on programmed CAS# latency.
2.
If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3.
Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4.
The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then
rounding up to the next higher integer.
5.
Minimum delay is required to complete write.
6.
All devices allow every cycle column address changes.
7.
In case of row precharge interrupt, auto precharge and read burst stop.
8.
A new command may be given tRFC after self-refresh exit.
SDRAM AC CHARACTERISTICS
Parameter
Symbol
125MHz
100MHz
83MHz
Units
Min
Max
Min
Max
Min
Max
Clock Cycle Time (1)
CL = 3
tCC
8
1000
10
1000
12
1000
ns
CL = 2
tCC
10
1000
12
1000
15
1000
ns
Clock to valid Output delay (1,2)
tSAC
67
8
ns
Output Data Hold Time (2)
tOH
33
3
ns
Clock HIGH Pulse Width (3)
tCH
33
3
ns
Clock LOW Pulse Width (3)
tCL
33
3
ns
Input Setup Time (3)
tSS
22
2
ns
Input Hold Time (3)
tSH
11
1
ns
CK to Output Low-Z (2)
tSLZ
22
2
ns
CK to Output High-Z
tSHZ
77
8
ns
Row Active to Row Active Delay (4)
tRRD
20
24
ns
RAS\ to CAS\ Delay (4)
tRCD
20
24
ns
Row Precharge Time (4)
tRP
20
24
ns
Row Active Time (4)
tRAS
50
10,000
50
10,000
60
10,000
ns
Row Cycle Time - Operation (4)
tRC
70
80
90
ns
Row Cycle Time - Auto Refresh (4,8)
tRFC
70
80
90
ns
Last Data in to New Column Address
Delay (5)
tCDL
11
1
CK
Last Data in to Row Precharge (5)
tRDL
11
1
CK
Last Data in to Burst Stop (5)
tBDL
11
1
CK
Column Address to Column Address
Delay (6)
tCCD
1.5
CK
Number of Valid Output Data (7)
2
ea
12
1
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