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參數(shù)資料
| 型號(hào)： | WED9LAPC2C16P8BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, PBGA153 |
| 封裝： | 14 X 22 MM, BGA-153 |
| 文件頁數(shù)： | 19/21頁 |
| 文件大?。?/td> | 693K |
| 代理商： | WED9LAPC2C16P8BI |
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2B16P8BC
November 2001
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
SDRAM CURRENT STATE TRUTH TABLE (continued)
Current State
Command
Action
Notes
BRAS or
PRAS
BCAS or
PCAS
BWE or
PWE
BADDR12,
BADDR13
or PBS
BADDR or
PADDR
Description
Write with
Auto Precharge
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
2
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
BA
Column
Write
ILLEGAL
H
L
H
BA
Column
Read
ILLEGAL
H
L
X
Burst Termination
ILLEGAL
H
X
No Operation
Continue the Burst
Precharging
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
No Operation; Bank(s) idle after tRP
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
BA
Column
Write w/o Precharge
ILLEGAL
2
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
20
H
L
X
Burst Termination
No Operation; Bank(s) idle after tRP
H
X
No Operation
No Operation; Bank(s) idle after tRP
Row Activating
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
2
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
BA
Column
Write
ILLEGAL
2
H
L
H
BA
Column
Read
ILLEGAL
2
H
L
X
Burst Termination
No Operation; Row active after tRCD
H
X
No Operation
No Operation; Row active after tRCD
Write Recovering
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
2
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
BA
Column
Write
Start Write; Determine if Auto Precharge
6
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
6
H
L
X
Burst Termination
No Operation; Row active after tDPL
H
X
No Operation
No Operation; Row active after tDPL
Write Recovering
with Auto
Precharge
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
2
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
BA
Column
Write
ILLEGAL
2,6
H
L
H
BA
Column
Read
ILLEGAL
2,6
H
L
X
Burst Termination
No Operation; Precharge after tDPL
H
X
No Operation
No Operation; Precharge after tDPL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED9LAPC2C16V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC2C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LC6416V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
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