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參數(shù)資料
| 型號(hào)： | WED9LAPC2C16P8BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, PBGA153 |
| 封裝： | 14 X 22 MM, BGA-153 |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 693K |
| 代理商： | WED9LAPC2C16P8BI |
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2B16P8BC
November 2001
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
SDRAM AC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
Clock Cycle Time (1)
CL = 3
tCC
8
1000
ns
CL = 2
tCC
10
1000
ns
Clock To Valid Output Delay (1,2)
tSAC
6ns
Output Data Hold Time (2)
tOH
2.5
ns
Clock High Pulse Width (3)
tCH
3ns
Clock Low Pulse Width (3)
tCL
3ns
Input Setup Time (3)
tSS
2ns
Input Hold Time (3)
tSH
1ns
Clk To Output Low-Z (2)
tSLZ
1ns
Clk To Output High-Z
tSHZ
6ns
Row Active To Row Active Delay (4)
tRRD
16
ns
RAS# To CAS# Delay (4)
tRCD
20
ns
Row Precharge Time (4)
tRP
20
ns
Row Active Time (4)
tRAS
48
10,000
ns
Row Cycle Time – Operation (4)
tRC
70
ns
Row Cycle Time – Auto Refresh (4,8)
tRFC
70
ns
Last Data In To New Column Address Delay (5)
tCDL
1
CLK
Last Data In To Row Precharge (5)
tRDL
2
CLK
Last Data In To Burst Stop (5)
tBDL
1
CLK
Column Address To Column Address Delay (6)
tCCD
1
CLK
Number Of Valid Output Data (7)
2EA
1EA
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If trise of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer.
5. Minimum delay is required to complete write.
6. Al devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self-refresh exit.
REFRESH CYCLE PARAMETERS
Parameter
Symbol
Min
Max
Units
Refresh Period1,2
tREF
—64
ms
NOTES:
1. 1024 cycles
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device.
CLOCK FREQUENCY AND LATENCY PARAMETERS
(Unit = number of clock)
Cycle Time
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
70ns
48ns
20ns
16ns
20ns
10ns
8.0ns
396323112
10.0ns
275222112
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED9LAPC2C16V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC2C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LC6416V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
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