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參數(shù)資料
| 型號(hào)： | WED3EG7234S202D3 |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大?。?/td> | 93K |
| 代理商： | WED3EG7234S202D3 |
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7234S-D3
May 2002
Rev. # 0
FINAL
White Electronic Designs Corp. reserves the right to change products or specications without notice.
IDD1 : OPERATING CURRENT: ONE
BANK
1. Typical Case : VDD = 2.5V, T = 25’C
2. Worst Case : VDD = 2.7V, T = 10’C
3. Only one bank is accessed with tRC (min), Burst Mode,
Address and Control inputs on NOP edge are changing
once per clock cycle.
Iout = 0mA
4. Timing patterns
-DDR200 (100Mhz, CL = 2) : tCK = 10ns, CL2, BL = 4,
tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same
timing with random address changing *50% of data
changing at every burst
-DDR266B (133Mhz, CL = 2.5): tCK = 7.5ns, CL = 2.5,
BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing *50% of
data changing at every burst
-DDR266A (133Mhz, CL = 2) : tCK = 7.5ns, CL = 2, BL
= 4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing*50% of
data changing at every burst
IDD7A : OPERATING CURRENT : FOUR
BANK OPERATION
1. Typical Case : VDD = 2.5V, T = 25’C
2. Worst Case : VDD = 2.7V, T = 10’C
3. Four banks are being interleaved with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are not
changing.
Iout = 0mA
4. Timing patterns
- DDR200 (100Mhz, CL = 2) : tCK = 10ns, CL2, BL =
4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 -
repeat the same timing with random address
changing *100% of data changing at every burst
-DDR266B (133Mhz, CL = 2.5) : tCK = 7.5ns, CL =
2.5, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing *100% of data changing at every burst
-DDR266A (133Mhz, CL = 2) : tCK = 7.5ns, CL2 = 2,
BL = 4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing *100% of data changing at every burst
Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
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| WED3EG72512SXX-AJD3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR SDRAM Modules - 184 Pin DIMM. Registered 72-bit wide |
| WED3EG72M18S202JD3IMG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED |
| WED3EG72M18S202JD3ISG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED |
| WED3EG72M18S202JD3MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED |
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