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| 型號(hào)： | WED3EG7234S202D3 |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 93K |
| 代理商： | WED3EG7234S202D3 |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7234S-D3
May 2002
Rev. # 0
FINAL
White Electronic Designs Corp. reserves the right to change products or specications without notice.
IDD SPECIFICATIONS AND TEST CONDITIONS
(Recommended operating conditions, TA = 0 to 70C, VDDQ = 2.5V+\-0.2V, VDD = 2.5V +\-0.2V)
* Module IDD was calculated on the basis of component IDD and can be different measured according to DQ loading cap.
Parameter
Symbol
Conditions
DDR266@CL=2
Max
DDR266@CL=2.5
Max
DDR200@CL=2
Max
Units
Operating Current
IDD0
One device bank; Active = Precharge;
TRC=TRC(MIN); TCK=TCK
(MIN); DQ, DM and DQS inputs changing
once per clock cycle; Address and control
inputs changing once every two cycles.
2660
2470
mA
Operating Current
IDD1
One device banks; Active-Read-Precharge;
Burst = 2; TRC=TRC(MIN); TCK=TCK
(MIN); lout=0mA; Address and control inputs
changing once per clock cycle.
2980
2800
mA
Precharge Power-
Down Standby Current
IDD2P
All device bank idle; Power-down mode;
TCK=TCK(MIN); CKE=(low)
1130
1120
mA
dle Standby Current
IDD2F
CS# = High; All device banks idle;
TCK=TCK(MIN); CKE = high; Address and
other control inputs changing once per clock
cycle. Vin = Vref for DQ, DQS and DM.
1460
1400
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode;
TCK(MIN); CKE=(low)
1620
1520
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device bank;
Active-Precharge; TRC=TRAS(MAX);
TCK=TCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle
1950
1790
mA
Operating Current
IDD4R
Burst = 2; Reads; Continous burst; Once
device bank active; Address and control
inputs changing once per clock cycle;
TCK=TCK(MIN); IOUT=0mA
3120
2750
mA
Operating Current
IDD4W
Burst=2; Writes; Continous burst; Once
device bank active; Address and control
inputs changing once per clock cycle;
TCK=TCK(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
3240
2790
mA
Auto Refresh Current
IDD5
TRC=TRC(MIN)
4080
mA
Self Refresh Current
IDD6
CKE < 0.2V
1140
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with
auto precharge with TRC=TRC(MIN);
TCK=TCK(MIN); Address and control input
change only during Active Read or Write
commands.
5890
4840
mA
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