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參數(shù)資料
| 型號： | WED3DG6435V75JD1-QG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA144 |
| 封裝： | ROHS COMPLIANT, SODIMM-144 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 157K |
| 代理商： | WED3DG6435V75JD1-QG |
WED3DG6435V-D1
-JD1
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
May 2007
Rev. 7
AC TIMING PARAMETERS
Symbol
Parameter
Speed Grade
100MHz
Speed Grade
133MHz
Units
Notes
Min
Max
Min
Max
tCK
Clock Period
10
7.5
ns
tCH
Clock High Time Rated @1.5V
3
2.5
ns
tCL
Clock Low Time
3
2.5
ns
tIS
Input Setup Times
Address/ Command & CKE
2
1.5
ns
Data
2
1.5
ns
tIH
Input Hold Times
Address/Command & CKE
1
0.8
ns
Data
1
0.8
ns
tAC
Output Valid From Clock
CAS# Latency = 2 or 3,
LVTTL levels, Rated @ 50
pF all outputs switching
5.4
(tco = 5.2)
5.4
(tco = 4.6)
ns
1
tOH
Output Hold From Clock Rated @ 50 pF (1.8 ns @ 0 pf)
3
ns
tOHZ
Output Valid to Z
3736
ns
tCCD
CAS to CAS Delay
1
tCK
tRP
RAS Precharge Time
15
ns
tRAS
RAS Active Time
37
ns
tRCD
Activate to Command Delay (RAS to CAS Delay)
15
ns
tRRD
RAS to RAS Bank Activate Delay
14
ns
tRC
RAS Cycle Time
60
ns
tDQD
DQM to Input Data Delay
0
tCK
tRSC
Mode Register set to Active delay
2
tCK
tROH
Precharge to O/P in High Z
CL = 2(2) (3) CL = 3 (2) CL = 2 3 CL = 3
tCK
2
tDQZ
DQM to Data in High Z for read
2222
tCK
tDQM
DQM to Data mask for write
0
tCK
3
tDPL
Data-in to PRE Command Period
2
tCK
tDAL
Data-in to ACT (PRE) Command period (Auto precharge)
4
tCK
tSB
Power Down Mode Entry
8
7
1
ns
tSRX
Self Refresh Exit Time
1
tCK
tPDE
Power Down Exit Set up Time
1
tCK
5
tREF
Refresh Period
64
ms
tRFC
Row Refresh Cycle Time
63
66
ns
1.
Access times to be measured w/input signals of 1 V/ns edge rate, 0.8 V to 2.0 V, tCO is clock to output with no load.
2.
CL = CAS Latency
3.
Data Masked on the same clock
4.
Self refresh Exit is asynchronous, requiring 10 ns to ensure initiation. Self refresh exit is complete in 10 ns + tRC.
5.
Timing is asynchronous. If tIS is not met by rising edge of CK then CKE is assumed latched on next cycle.
6.
If the clock is stopped during self refresh or power down, 200 clocks are required before CKE is high.
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| WED3DG6435V7AD1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 SDRAM UNBUFFERED |
| WED3DG6435V7D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 SDRAM UNBUFFERED |
| WED3DG6435V7JD1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 SDRAM UNBUFFERED |
| WED3DG6435V-AD1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 SDRAM UNBUFFERED |
| WED3DG6435V-D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 SDRAM UNBUFFERED |
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