參數(shù)資料
型號: WED2ZL362MS30BC
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: SRAM
英文描述: 2M X 36 MULTI DEVICE SRAM MODULE, 3 ns, PBGA119
封裝: PLASTIC, BGA-119
文件頁數(shù): 6/12頁
文件大?。?/td> 272K
代理商: WED2ZL362MS30BC
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED2ZL362MS
CEx
ADV
WE
BWx
OE
CKE
CLK
Address Accessed
Operation
HL
XXX
L
N/A
Deselect
XHXXX
L
N/A
Continue Deselect
LL
H
XLL
External Address
Begin Burst Read Cycle
XHXX
L
Next Address
Continue Burst Read Cycle
LL
H
XH
L
External Address
NOP/Dummy Read
XHXXH
L
Next Address
Dummy Read
LLLL
XL
External Address
Begin Burst Write Cycle
X
HXL
XL
Next Address
Continue Burst Write Cycle
LLL
H
XL
N/A
NOP/Write Abort
XHXHX
L
Next Address
Write Abort
XXXXXH
Current Address
Ignore Clock
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
WRITE TRUTH TABLE
WE
BWa
BWb
BWc
BWd
Operation
H
XXXX
Read
L
H
Write Byte a
L
H
L
H
Write Byte b
L
H
L
H
Write Byte c
L
H
L
Write Byte d
LLLLL
Write All Bytes
L
HHHH
Write Abort/NOP
NOTES:
1. X means Dont Care.
2. All inputs in this table must meet setup and hold time around the rising edge of CLK ( ).
NOTES:
1. X means Dont Care.
2. The rising edge of clock is symbolized by ( )
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins (ZZ and OE).
6. CEx refers to the combination of CE1, CE2 and CE2.
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