參數(shù)資料
型號: WE32K32-80G1TI
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: PROM
英文描述: 32K X 32 EEPROM 5V MODULE, 80 ns, CQFP68
封裝: 23.90 MM, CERAMIC, QFP-68
文件頁數(shù): 9/14頁
文件大?。?/td> 204K
代理商: WE32K32-80G1TI
4
WhiteElectronicDesignsCorporationPhoenix,AZ(602)437-1520
White Electronic Designs
WE32K32-XXX
WRITE
AC WRITE CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C TO +125°C)
WRITE CYCLE
-80-90-120-150
Write Cycle Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Write Cycle Time, TYP = 6ms
tWC
10
ms
Address Set-up Time
tAS
0
30
ns
Write Pulse Width (WE or CS)
tWP
100
150
ns
Chip Select Set-up Time
tCS
00
0
ns
Address Hold Time
tAH
50
100
ns
Data Hold Time
tDH
0
10
ns
Chip Select Hold Time
tCSH
00
0
ns
Data Set-up Time
tDS
50
100
ns
Write Pulse Width High
tWPH
50
ns
Output Enable Set-up Time
tOES
10
ns
Output Enable Hold Time
tOEH
10
ns
A write cycle is initiated when OE is high and a low pulse
is on WE or CS with CS or WE low. The address is
latched on the falling edge of CS or WE whichever oc-
curs last. The data is latched by the rising edge of CS
or WE, whichever occurs first. A byte write operation
will automatically continue to completion.
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relation-
ships. A write cycle begins with address application,
write enable and chip select. Chip select is accom-
plished by placing the CS line low. Write enable con-
sists of setting the WE line low. The write cycle begins
when the last of either CS or WE goes low.
The WE line transition from high to low also initiates an
internal 150 sec delay timer to permit page mode op-
eration. Each subsequent WE transition from high to
low that occurs before the completion of the 150 sec
time out will restart the timer from zero. The operation
of the timer is the same as a retriggerable one-shot.
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