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參數(shù)資料
| 型號： | W986432DH-8 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86 |
| 封裝： | 0.400 INCH, 0.50 MM PITCH, TSOP2-86 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 77K |
| 代理商： | W986432DH-8 |
W986432DH
Publication Release Date: May 2000
- 7 -
Revision A0
AC CHARACTERISTICS
(VCC = 3.3V
± 0.3V, VSS = 0V, Ta = 0 to 70 °C) (Notes: 5, 6.)
PARAMETER
Symbol
-5
-55
-6
UNIT
NOTE
MIN
MAX
MIN
MAX
MIN
MAX
Ref/Active to Ref/Active Command Period tRC
54
55
60
ns
Active to precharge Command Period
tRAS
40
100000
40
100000
42
100000
Active to Read/Write Command Delay TimetRCD
14
15
18
Read/Write(a) to Read/Write(b)Command
Period
tCCD
1
Cycle
Precharge to Active(b) Command Period
tRP
14
15
18
ns
Active(a) to Active(b) Command Period
tRRD
10
10.8
12
Write Recovery Time
CL* = 2
tWR
7
7.5
CL* = 3
5
5.4
6
CLK Cycle Time
CL* = 2
tCK
7
1000
7.5
1000
7.5
1000
CL* = 3
5
1000
5.4
1000
6
1000
CLK High Level
tCH
2
CLK Low Level
tCL
2
Access Time from CLK
CL* = 2 tAC
4.5
5.5
CL* = 3
4.5
5
Output Data Hold Time
tOH
2.75
Output Data High Impedance Time
tHZ
2.75
5
2.75
5.4
2.75
6
Output Data Low Impedance Time
tLZ
0
Power Down Mode Entry Time
tSB
0
5
0
5.4
0
6
Transition Time of CLK (Rise and Fall)
tT
0.5
10
0.5
10
0.5
10
Data-in-Set-up Time
tDS
1
1.5
Data-in Hold Time
tDH
0.5
Address Set-up Time
tAS
1.3
1.5
Address Hold Time
tAH
0.8
1
0.5
CKE Set-up Time
tCKS
1.3
1.5
CKE Hold Time
tCKH
0.8
1
0.5
Command Set-up Time
tCMS
1
1.5
Command Hold Time
tCMH
0.5
Refresh Time
tREF
64
ms
Mode Register Set Cycle Time
tRSC
10
10.8
12
ns
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相關代理商/技術參數(shù) |
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