參數(shù)資料
型號： W986432DH-7L
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝： 0.400 INCH, 0.50 MM PITCH, TSOP2-86
文件頁數(shù)： 8/48頁
文件大?。?/td> 1648K
代理商： W986432DH-7L
W986432DH
- 16 -
14. AC CHARACTERISTICS
(VCC = 3.3V
±0.3V, VSS = 0V, TA = 0 to 70° C for -5/-6/-7/-7L,TA = -40 to 85° C for -6I) (Notes: 5, 6.)
-5
-6/-6I
-7/-7L
PARAMETER
SYM.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
NOTE
Ref/Active to Ref/Active Command Period
tRC
54
60
65
nS
Active to precharge Command Period
tRAS
40
100000
42
100000
45
100000
Active to Read/Write Command Delay Time
tRCD
14
18
20
Read/Write(a) to Read/Write(b) Command
Period
tCCD
1
Cycle
Precharge to Active(b) Command Period
tRP
14
18
20
nS
Active(a) to Active(b) Command Period
tRRD
10
12
14
7
7.5
8
Wreite Recovery Time
CL* = 2
CL* = 3
tWR
5
6
7
1000
7.5
1000
8
1000
CLK Cycle Time
CL* = 2
CL* = 3
tCK
5
1000
6
1000
7
1000
CLK High Level
tCH
2
CLK Low Level
tCL
2
5.5
6
Access Time from CLK
CL* = 2
CL* = 3
tAC
4.5
5
5.5
Output Data Hold Time
tOH
1.5
2
Output Data High Impedance Time
tHZ
1.5
5
2
6
2
7
Output Data Low Impedance Time
tLZ
0
Power Down Mode Entry Time
tSB
0
5
0
6
0
7
Transition Time of CLK (Rise and Fall)
tT
0.5
10
0.5
10
0.5
10
Data-in-Set-up Time
tDS
1.5.
1.5
Data-in Hold Time
tDH
1
Address Set-up Time
tAS
1.5
Address Hold Time
tAH
1
CKE Set-up Time
tCKS
1.5
CKE Hold Time
tCKH
1
Command Set-up Time
tCMS
1.5
Command Hold Time
tCMH
1
Refresh Time
tREF
64
mS
Mode Register Set Cycle Time
tRSC
10
12
14
nS
Notes:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK
and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with output open.
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