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參數(shù)資料
| 型號： | W9751G8JB-18 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA84 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大小： | 1458K |
| 代理商： | W9751G8JB-18 |
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8) ASO - Area of Safety Operation
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
9) Built-in thermal shutdown (TSD) circuit
The TSD circuit is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or
guarantee its operation in the presence of extreme heat. Do not continue to use the IC after the TSD circuit is activated,
and do not operate the IC in an environment where activation of the circuit is assumed.
10) Capacitor between output and GND
In the event a large capacitor is connected between the output and GND, if VCC and VIN are short-circuited with 0V or
GND for any reason, the current charged in the capacitor flows into the output and may destroy the IC. Use a capacitor
smaller than 1μF between output and GND.
11) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a low impedance pin subjects the IC to stress.
Therefore, always discharge capacitors after each process or step. Always turn the IC's power supply off before
connecting it to or removing it from the test setup during the inspection process. Ground the IC during assembly steps
as an antistatic measure. Use similar precaution when transporting or storing the IC.
12) Switching noise
When the operation mode is in PWM control or VREF control, PWM switching noise may effects to the control input
pins and cause IC malfunctions. In this case, insert a pulled down resistor (10k
is recommended) between each
control input pin and ground.
13) Regarding the input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements, in order to keep them
isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic
diode or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, as well as operating malfunctions and physical damage. Therefore, do not use methods
by which parasitic diodes operate, such as applying a voltage lower than the GND (P substrate) voltage to an input pin.
Ordering part number
B
D
6
2
X
-
ROHM part
number
Type
1X: 7V max.
2X: 18V max.
3X: 36V max.
X0: 1ch/0.5A X5: 2ch/0.5A
X1: 1ch/1A
X6: 2ch/1A
X2: 1ch/2A
X7: 2ch/2A
Package
F: SOP8
FV: SSOPB24
FP: HSOP25
FM: HSOPM28
HFP: HRP7
Packaging spec.
E2: Embossed taping
(SOP8/SSOPB24
/HSOP25/HSOPM28)
TR: Embossed taping
(HRP7)
Resistor
Transistor (NPN)
N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin A
N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin B
C
B
E
N
GND
Pin A
Parasitic
element
Pin B
Other adjacent elements
E
B
C
GND
Parasitic
element
Appendix: Example of monolithic IC structure
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