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參數(shù)資料
| 型號： | W9712G8JB-3 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA60 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60 |
| 文件頁數(shù)： | 13/86頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | W9712G8JB-3 |
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W9712G8JB
Publication Release Date: Oct. 12, 2010
- 20 -
Revision A01
7.3 Command Function
7.3.1
Bank Activate Command
( CS = "L", RAS = "L", CAS = "H", WE = "H", BA0, BA1 = Bank, A0 to A11 be row address)
The Bank Activate command must be applied before any Read or Write operation can be executed.
Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command
on the following clock cycle. If a Read/Write command is issued to a bank that has not satisfied the
tRCDmin specification, then additive latency must be programmed into the device to delay when the
Read/Write command is internally issued to the device. The additive latency value must be chosen to
assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 and 6 are supported. Once a bank has
been activated it must be precharged before another Bank Activate command can be applied to the
same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The
minimum time interval between successive Bank Activate commands to the same bank is determined
by the RAS cycle time of the device (tRC). The minimum time interval between Bank Activate
commands is tRRD.
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr.
Bank A
Addr.
Bank B
Addr.
Bank A
Row Addr.
CAS - CAS delay time(tCCD)
tRCD = 1
Additive Latency delay(AL)
Read Begins
Bank A
Activate
Bank A
Post CAS
Read
Bank B
Activate
Bank B
Post CAS
Read
Bank A
Precharge
Bank B
Precharge
Bank A
Activate
Bank Active (≥ tRAS)
RAS Cycle time (≥ tRC)
Bank Precharge time (≥ tRP)
Command
Address
RAS - RAS delay time(≥ tRRD)
CLK
Internal RAS - RAS delay (≥ tRCDmin)
Figure 12 – Bank activate command cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
7.3.2
Read Command
( CS = "L", RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A10 = "L", A0 to A9 = Column
Address)
The READ command is used to initiate a burst read access to an active row. The value on BA0, BA1
inputs selects the bank, and the A0 to A9 address inputs determine the starting column address. The
address input A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected,
the row being accessed will be precharged at the end of the READ burst; if Auto-precharge is not
selected, the row will remain open for subsequent accesses.
7.3.3
Write Command
( CS = "L", RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "L", A0 to A9 = Column
Address)
The WRITE command is used to initiate a burst write access to an active row. The value on BA0, BA1
inputs selects the bank, and the A0 to A9 address inputs determine the starting column address. The
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| W971GG6JB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 8 BANKS ? 16 BIT DDR2 SDRAM |
| W971GG6JB-18 | 制造商:Winbond Electronics Corp 功能描述:1GB DDR2 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 1GBIT 1.875NS |
| W971GG6JB-25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:64MBX16 DDR2 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA |
| W971GG6JB25I | 功能描述:IC DDR2 SDRAM 1GBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR |
| W971GG6JB-25I | 制造商:Winbond Electronics 功能描述:-40~85 1GB DDR2 FOR INDUSTRY |
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