參數(shù)資料
型號: W3HG2128M72EER534D4SG
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 256M X 72 MULTI DEVICE DRAM MODULE, ZMA200
封裝: ROHS COMPLIANT, DIMM-200
文件頁數(shù): 9/11頁
文件大小: 162K
代理商: W3HG2128M72EER534D4SG
W3HG2128M72EER-D4
October 2006
Rev. 1
CONCEPT
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DDR2 SDRAM COMPONENTAC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Clock
Clock cycle time
CL = 6
tCK (6)
ps
CL = 5
tCK (5)
ps
CL = 4
tCK (4)
ps
CL = 3
tCK (3)
ps
CK high-level width
tCH
tCK
CK low-level width
tCL
tCK
Half clock period
tHP
ps
Clock jitter
tJIT
ps
Data
DQ output access time from CK/CK#
tAC
ps
Data-out high-impedance window from
CK/CK#
tHZ
ps
Data-out low-impedance window from
CK/CK#
tLZ
ps
DQ and DM input setup time relative to
DQS
tDS
ps
DQ and DM input hold time relative to DQS
tDH
ps
DQ and DM input pulse width (for each
input)
tDIPW
tCK
Data hold skew factor
tQHS
ps
DQ…DQS hold, DQS to rst DQ to go
nonvalid, per access
tQH
ps
Data valid output window (DVW)
tDVW
ns
Data
Strobe
DQS input high pulse width
tDQSH
tCK
DQS input low pulse width
tDQSL
tCK
DQS output access time from CK/CK#
tDQSCK
ps
DQS falling edge to CK rising … setup time
tDSS
tCK
DQS falling edge from CK rising … hold
time
tDSH
tCK
DQS…DQ skew, DQS to last DQ valid, per
group, per access
tDQSQ
ps
DQS read preamble
tRPRE
tCK
DQS read postamble
tRPST
tCK
DQS write preamble setup time
tWPRES
p s
DQS write preamble
tWPRE
tCK
DQS write postamble
tWPST
tCK
Write command to rst DQS latching
transition
tDQSS
tCK
Address and control input pulse width for
each input
tIPW
tCK
Address and control input setup time
tIS
ps
Address and control input hold time
tIH
ps
Address and control input hold time
tCCD
tCK
AC specication is based on
xxxx components. Other DRAM manufactures specication may be different.
Continued on next page
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