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參數(shù)資料
| 型號： | W3HG2128M72EER534D4SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 MULTI DEVICE DRAM MODULE, ZMA200 |
| 封裝： | ROHS COMPLIANT, DIMM-200 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 162K |
| 代理商： | W3HG2128M72EER534D4SG |
W3HG2128M72EER-D4
October 2006
Rev. 1
CONCEPT
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DDR2 SDRAM COMPONENTAC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Command
and
Address
ACTIVE to ACTIVE (same bank) command
tRC
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
ns
ACTIVE to READ or WRITE delay
tRCD
ns
Four Bank Activate period
tFAW
ns
ACTIVE to PRECHARGE command
tRAS
ns
Internal READ to precharge command delay
tRTP
ns
Write recovery time
tWR
ns
Auto precharge write recovery + precharge
time
tDAL
ns
Internal WRITE to READ command delay
tWTR
ns
PRECHARGE command period
tRP
ns
PRECHARGE ALL command period
tRPA
ns
LOAD MODE command cycle time
tMRD
tCK
CKE low to CK,CK# uncertainty
tDELAY
ns
Self
Refresh
REFRESH to Active of Refresh to Refresh
command interval
tRFC
ns
Average periodic refresh interval
tREFI
s
Exit self refresh to non-READ command
tXSNR
ns
Exit self refresh to READ command
tXSRD
tCK
Exit self refresh timing reference
tISXR
ps
ODT
ODT turn-on delay
tAOND
tCK
ODT turn-on
tAON
ps
ODT turn-off delay
tAOFD
tCK
ODT turn-off
ps
ODT turn-on (power-down mode)
tAONPD
ps
ODT turn-off (power-down mode)
tAOFPD
ps
ODT to power-down entry latency
tANPD
tCK
ODT power-down exit latency
tAXPD
tCK
Power-Down
Exit active power-down to READ command,
MR[bit12=0]
tXARD
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
tCK
A Exit precharge power-down to any non-
READ command.
tXP
tCK
CKE minimum high/low time
tCKE
tCK
AC specication is based on
xxxx components. Other DRAM manufactures specication may be different.
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