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參數(shù)資料
| 型號： | W3H64M72E-400SBM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
| 封裝： | 16 X 22 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 944K |
| 代理商： | W3H64M72E-400SBM |
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W3H64M72E-XSBX
W3H64M72E-XSBXF
14
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
December 2009
2010 White Electronic Designs Corp. All rights reserved
Rev. 9
White Electronic Designs Corp. reserves the right to change products or specications without notice.
0
1
0
1
Mode Register Definition
M16
0
0
1
M15
High Temperature Self Refresh rate enable
Industrial temperature option;
use if T
C ex cee ds 85° C
E7
0
1
M17
0
0
Mode register (MR)
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
Commercial temperature default
A9
A7 A6 A5 A4 A3
A8
A2
A1 A0
Extended Mode
Register (Ex)
Address Bus
97
6
5
4
3
82
1
0
A10
A12
A11
BA0
BA1
10
11
12
13
0
00
0
14
15
A13
A14
EMR2
BA2
16
17
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make
the command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. Bits E3–E5 dene the value
of AL, as shown in Figure 7. Bits E3–E5 allow the user
to program the DDR2 SDRAM with an inverse AL of 0, 1,
2, 3, or 4 clocks. Reserved states should not be used as
unknown operation or incompatibility with future versions
may result.
In this operation, the DDR2 SDRAM allows a READ or
WRITE command to be issued prior to tRCD (MIN) with
the requirement that AL ≤ tRCD (MIN). A typical application
using this feature would set AL = tRCD (MIN) - 1x tCK. The
READ or WRITE command is held for the time of the AL
before it is issued internally to the DDR2 SDRAM device.
RL is controlled by the sum of AL and CL; RL = AL+CL.
Write latency (WL) is equal to RL minus one clock; WL =
AL + CL - 1 x tCK.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W3H64M72E-533ES | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SB | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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