- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄203627 > W3H32M72E-533SB2C (WHITE ELECTRONIC DESIGNS CORP) 32M X 72 DDR DRAM, 0.65 ns, PBGA208 PDF資料下載
參數(shù)資料
| 型號： | W3H32M72E-533SB2C |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM, 0.65 ns, PBGA208 |
| 封裝： | 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 28/30頁 |
| 文件大?。?/td> | 0K |
| 代理商： | W3H32M72E-533SB2C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁
W3H32M72E-XSB2X
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
November 2009
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
low level must be applied to the ODT ball (all other
inputs may be undened, I/Os and outputs must be
less than VCCQ during voltage ramp time to avoid
DDR2 SDRAM device latch-up). At least one of the
following two sets of conditions (A or B) must be
met to obtain a stable supply state (stable supply
dened as VCC, VCCQ, VREF, and VTT are between
their minimum and maximum values as stated in
Table 20):
A. (single power source) The VCC voltage ramp
from 300mV to VCC (MIN) must take no longer
than 200ms; during the VCC voltage ramp, |VCC
-
VCCQ| ≤ 0.3V. Once supply voltage ramping
is complete (when VCCQ crosses VCC (MIN)),
Table20 specications apply.
VCC, VCCQ are driven from a single power
converter output
VTT is limited to 0.95V MAX
VREF tracks VCCQ/2; VREF must be within
±0.3V with respect to VCCQ/2 during supply
ramp time
VCCQ ≥ VREF at all times
B. (multiple power sources) VCC ≥ VCCQ must be
maintained during supply voltage ramping, for
both AC and DC levels, until supply voltage
ramping completes (VCCQ crosses VCC [MIN]).
Once supply voltage ramping is complete,
Table20 specications apply.
Apply VCC before or at the same time as
VCCQ; VCC voltage ramp time must be ≤
200ms from when VCC ramps from 300mV to
VCC (MIN)
Apply VCCQ before or at the same time as
VTT; the VCCQ voltage ramp time from when
VCC (MIN) is achieved to when VCCQ (MIN)
is achieved must be ≤ 500ms; while VCC is
ramping, current can be supplied from VCC
through the device to VCCQ
VREF must track VCCQ/2, VREF must be within
±0.3V with respect to VCCQ/2 during supply
ramp time; VCCQ ≥ VREF must be met at all
times
Apply VTT; The VTT voltage ramp time from
when VCCQ (MIN) is achieved to when VTT
(MIN) is achieved must be no greater than
500ms
2.
For a minimum of 200μs after stable power nd clock
(CK, CK#), apply NOP or DESELECT commands
and take CKE HIGH.
3.
Wait a minimum of 400ns, then issue a
PRECHARGE ALL command.
4.
Issue an LOAD MODE command to the EMR(2).
(To issue an EMR(2) command, provide LOW to
BA0, provide HIGH to BA1.)
5.
Issue a LOAD MODE command to the EMR(3). (To
issue an EMR(3) command, provide HIGH to BA0
and BA1.)
6.
Issue an LOAD MODE command to the EMR to
enable DLL. To issue a DLL ENABLE command,
provide LOW to BA1 and A0, provide HIGH to BA0.
Bits E7, E8, and E9 can be set to “0” or “1”; Micron
recommends setting them to “0.”
7.
Issue a LOAD MODE command for DLL RESET.
200 cycles of clock input is required to lock the
DLL. (To issue a DLL RESET, provide HIGH to A8
and provide LOW to BA1, and BA0.) CKE must be
HIGH the entire time.
8.
Issue PRECHARGE ALL command.
9.
Issue two or more REFRESH commands, followed
by a dummy WRITE.
10. Issue a LOAD MODE command with LOW to A8 to
initialize device operation (i.e., to program operating
parameters without resetting the DLL).
11. Issue a LOAD MODE command to the EMR to
enable OCD default by setting bits E7, E8, and E9
to “1,” and then setting all other desired parameters.
12. Issue a LOAD MODE command to the EMR to
enable OCD exit by setting bits E7, E8, and E9 to
13. Issue a LOAD MODE command with LOW to A8 to
initialize device operation (i.e., to program operating
parameters without resetting the DLL).
14. Issue a LOAD MODE command to the EMR to
enable OCD default by setting bits E7,E8, and E9 to
“1,” and then setting all other desired parameters.
15. Issue a LOAD MODE command to the EMR to
enable OCD exit by setting bits E7, E8, and E9 to
“0,” and then setting all other desired parameters.
The DDR2 SDRAM is now initialized and ready for
normal operation 200 clocks after DLL RESET (in step 7).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3H32M72E-400SB2M | 32M X 72 DDR DRAM, 0.6 ns, PBGA208 |
| W3HG2128M72AER403AD6SG | 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| W3HG2128M72AER534AD6MG | 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| W3HG2128M72AER665AD6SG | 256M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| W3HG2128M72AER534AD6SG | 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3H32M72E-533SB2I | 制造商:Microsemi Corporation 功能描述:MICROCIRCUIT, DIGITAL, DDR2SDRAM, 2GB - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H32M72E-533SBC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H32M72E-533SBI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 533MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk |
| W3H32M72E-533SBM | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 533MHZ, 208PBGA MIL-TEMP. - Bulk |
| W3H32M72E-667ES | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。